Bias dependence of a deep submicron NMOSFET response to total dose irradiation

Deep submicron n-channel metal-oxide-semiconductor field-effect transistors (NMOSFETs) with shallow trench isolation (STI) are exposed to ionizing dose radiation under different bias conditions.The total ionizing dose radiation induced subthreshold leakage current increase and the hump effect under four different irradiation bias conditions including the worst case (ON bias) for the transistors are discussed.The high electric fields at the corners are partly responsible for the subthreshold hump effect.Charge trapped in the isolation oxide,particularly at the Si/SiO 2 interface along the sidewalls of the trench oxide creates a leakage path,which becomes a dominant contributor to the offstate drain-to-source leakage current in the NMOSFET.Non-uniform charge distribution is introduced into a threedimensional (3D) simulation.Good agreement between experimental and simulation results is demonstrated.We find that the electric field distribution along with the STI sidewall is important for the radiation effect under different bias conditions.     

Study of total ionizing dose radiation effects on enclosed gate transistors in a commercial CMOS technology

This paper studies the total ionizing dose radiation effects on MOS （metal-oxide-semiconductor） transistors with normal and enclosed gate layout in a standard commercial CMOS （compensate MOS） bulk process. The leakage current, threshold voltage shift, and transconductance of the devices were monitored before and after γ-ray irradiation. The parameters of the devices with different layout under different bias condition during irradiation at different total dose are investigated. The results show that the enclosed layout not only effectively eliminates the leakage but also improves the performance of threshold voltage and transconductance for NMOS （n-type channel MOS） transistors. The experimental results also indicate that analogue bias during irradiation is the worst case for enclosed gate NMOS. There is no evident different behaviour observed between normal PMOS （p-type channel MOS） transistors and enclosed gate PMOS transistors.     

Gate-modulated generation–recombination current in n-type metal–oxide–semiconductor field-effect transistor

Gate-modulated generation–recombination（GMGR） current IGMGRinduced by the interface traps in an n-type metal–oxide–semiconductor field-effect transistor（n MOSFET） is investigated. The generation current is found to expand rightwards with increasing the reversed drain PN junction bias, and the recombination current is enhanced as the forward drain bias increases. The variations of IGMGRcurves are ascribed to the changes of the electron density and hole density at the interface, NSand PS, under the different drain bias voltages. Based on an analysis of the physical mechanism, the IGMGR model is set up by introducing two coefficients（m and t）. The coefficients m and t can modulate the curves widths and peak values. The simulated results under reverse mode and forward mode are obviously in agreement with the experimental results. This proves that this model can be applicable for generation current and recombination current and that the theory behind the model is reasonable. The details of the relevant mechanism are given in the paper.     

Total dose radiation and annealing responses of the back transistor of Silicon-On-Insulator pMOSFETs

The total dose radiation and annealing responses of the back transistor of Silicon-On-Insulator(SOI)pMOSFETs have been studied by comparing them with those of the back transistor of SOI n MOSFETs fabricated on the same wafer. The transistors were irradiated by60 Co γ-rays with various doses and the front transistors were biased in a Float-State and Off-State, respectively, during irradiation. The total dose radiation responses of the back transistors were characterized by their threshold voltage shifts. The results show that the total dose radiation response of the back transistor of SOI pMOSFETs, similar to that of SOI n MOSFETs, depends greatly on their bias conditions during irradiation. However, with the Float-State bias rather than the Off-State bias, the back transistors of SOI pMOSFETs reveal a much higher sensitivity to total dose radiation, which is contrary to the behavior of SOI n MOSFETs. In addition, it is also found that the total dose radiation effect of the back transistor of SOI pMOSFETs irradiated with Off-State bias, as well as that of the SOI n MOSFETs, increases as the channel length decreases. The annealing response of the back transistors after irradiation at room temperature without bias, as characterized by their threshold voltage shifts, indicates that there is a relatively complex annealing mechanism associated with channel length, type, and bias condition during irradiation. In particular, for all of the transistors irradiated with Off-State bias, their back transistors show an abnormal annealing effect during early annealing. All of these results have been discussed and analyzed in detail by the aid of simulation.     

Influence of dry-etching damage on the electrical properties of an AlGaN/GaN Schottky barrier diode with recessed anode

The influences of dry-etching damage on the electrical properties of an AlGaN/GaN Schottky barrier diode with ICPrecessed anode was investigated for the first time. It was found that the turn-on voltage is decreased with the increase of dry-etching power. Furthermore, the leakage currents in the reverse bias region above pinch-off voltage rise as radio frequency(RF) power increases, while below pinch-off voltage, leakage currents tend to be independent of RF power.Based on detailed current–voltage–temperature(I–V –T) measurements, the barrier height of thermionic-field emission(TFE) from GaN is lowered as RF power increases, which results in early conduction. The increase of leakage current can be explained by Frenkel–Poole(FP) emission that higher dry-etching damage in the sidewall leads to the higher tunneling current, while below pinch-off voltage, the leakage is only related to the AlGaN surface, which is independent of RF power.     

Corner effects in double-gate/gate-all-around MOSFETs

Two kinds of corner effects existing in double-gate （DG） and gate-all-around （GAA） MOSFETs have been investigated by three-dimensional （3D） and two-dimensional （2D） simulations. It is found that the corner effect caused by conterminous gates, which is usually deemed to deteriorate the transistor performance, does not always play a negative role in GAA transistors. It can suppress the leakage current of transistors with low channel doping, though it will enhance the leakage current at high channel doping. The study of another kind of corner effect, which exists in the corner at the bottom of the silicon pillar of DG/GAA vertical MOSFETs, indicates that the D-top structure with drain on the top of the device pillar of vertical transistor shows great advantage due to lower leakage current and better DIBL （drain induced barrier lowering） effect immunity than the S-top structure with source on the top of the device pillar. Therefore the D-top structure is more suitable when the requirement in leakage current and short channel character is critical.     

Investigation of the characteristics of GIDL current in 90nm CMOS technology

A specially designed experiment is performed for investigating gate-induced drain leakage （GIDL） current in 90nm CMOS technology using lightly-doped drain （LDD） NMOSFET. This paper shows that the drain bias VD has a strong effect on GIDL current as compared with the gate bias VG at the same drain-gate voltage VDG. It is found that the difference between ID in the off-state ID - VG characteristics and the corresponding one in the off-state ID - VD characteristics, which is defined as IDIFF, versus VDG shows a peak. The difference between the influences of VD and VG on GIDL current is shown quantitatively by IDIFF, especially in 90nm scale. The difference is due to different hole tunnellings, Furthermore, the maximum IDIFF（IDIFF,MAX） varies linearly with VDG in logarithmic coordiuates and also VDG at IDIFF,MAX with VF which is the characteristic voltage of IDIFF, The relations are studied and some related expressions are given.     

Role of Ga vacancies in enhancing the leakage current of GaN Schottky barrier ultraviolet photodetectors

The leakage current of GaN Schottky barrier ultraviolet photodetectors is investigated.It is found that the photodetectors adopting undoped GaN instead of lightly Si-doped GaN as an active layer show a much lower leakage current even when they have a higher dislocation density.It is also found that the density of Ga vacancies in undoped GaN is much lower than in Si-doped GaN.The Ga vacancies may enhance tunneling and reduce effective Schottky barrier height,leading to an increase of leakage current.It suggests that when undoped GaN is used as the active layer,it is necessary to reduce the leakage current of GaN Schottky barrier ultraviolet photodetector.     

Fabrication and Characteristics of AIInN/A1N/GaN MOS-HEMTs with Ultra-Thin Atomic Layer Deposited Al2O3 Gate Dielectric

Al0.85In0.15N//AlN/GaN metal-oxide-semiconductor high electron mobility transistors （MOS-HEMTs） employing a 3-nm ultra-thin atomic-layer deposited （ALD） Al2O3 gate dielectric layer are reported. Devices with 0.6μm gate lengths exhibit an improved maximum drain current density of 1227mA/mm at a gate bias of 3 V, a peak transeonductance of 328mS/mm, a cutoff frequency fr of 16 GHz, a maximum frequency of oscillation fmax of 45 GHz, as well as significant gate leakage suppression in both reverse and forward directions, compared with the conventionM Al0.85In0.15N/AlN/GaN HEMT. Negligible C - V hysteresis, together with a smaller pinch-off voltage shift, is observed, demonstrating few bulk traps in the dielectric and high quality of the Al2O3/AIInN interface, it is most notable that not only the transconductance profile of the MOS-HEMT is almost the same as that of the conventional HEMT with a negative shift, but also the peak transconduetance of the MOS-HEMT is increased slightly. It is an exeitin~ inwrovement in the transconductance performance.     

Study on the degradation of NMOSFETs with ultra-thin gate oxide under channel hot electron stress at high temperature

This paper studies the degradation of device parameters and that of stress induced leakage current (SILC) of thin tunnel gate oxide under channel hot electron (CHE) stress at high temperature by using n-channel metal oxide semiconductor field effect transistors (NMOSFETs) with 1.4-nm gate oxides.The degradation of device parameters under CHE stress exhibits saturating time dependence at high temperature.The emphasis of this paper is on SILC of an ultra-thin-gate-oxide under CHE stress at high temperature.Based on the experimental results,it is found that there is a linear correlation between SILC degradation and V h degradation in NMOSFETs during CHE stress.A model of the combined effect of oxide trapped negative charges and interface traps is developed to explain the origin of SILC during CHE stress.     

Investigating the effects of the interface defects on the gate leakage current in MOSFETs

The effects of the interface defects on the gate leakage current have been numerically modeled. The results demonstrate that the shallow and deep traps have different effects on the dependence relation of the stress-induced leakage current on the oxide electric field in the regime of direct tunneling, whereas both traps keep the same dependence relation in the regime of Fowler-Nordheim tunneling. The results also shows that the stress-induced leakage current will be the largest at a moderate oxide voltage for the electron interface traps but it increases with the decreasing oxide voltage for the hole interface traps. The results illustrate that the stress-induced leakage current strongly depends on the location of the electron interface traps but it weakly depends on the location of the hole interface traps. The increase in the gate leakage current caused by the electron interface traps can predict the increase, then decrease in the stress-induced leakage current, with decreasing oxide thickness, which is observed experimentally. And the electron interface trap level will have a large effect on the peak height and position.     

深亚微米器件沟道长度对总剂量辐照效应的影响

研究了180 nm 互补金属氧化物半导体技术下的器件沟道长度对总剂量辐照效应的影响. 在其他条件如辐照偏置、器件结构等不变的情况下, 氧化层中的陷阱电荷决定了辐照响应. 浅沟槽隔离氧化层中的陷阱电荷使得寄生的侧壁沟道反型, 从而形成大的关态泄漏电流. 这个电流与沟道长度存在一定的关系, 沟道长度越短, 泄漏电流越大. 首次发现辐照会增强这个电流的沟道长度调制效应, 从而使得器件进一步退化.     

小尺寸应变Si金属氧化物半导体场效应晶体管栅隧穿电流预测模型

小尺寸金属氧化物半导体场效应晶体管(MOSFET)器件由于具有超薄的氧化层、关态栅隧穿漏电流的存在严重地影响了器件的性能,应变硅MOSFET器件也存在同样的问题.为了说明漏电流对新型应变硅器件性能的影响,文中利用积分方法从准二维表面势分析开始,提出了小尺寸应变硅MOSFET栅隧穿电流的理论预测模型,并在此基础上使用二维器件仿真软件ISE进行了仔细的比对研究,定量分析了在不同栅压、栅氧化层厚度下MOSFET器件的性能.仿真结果很好地与理论分析相符合,为超大规模集成电路的设计提供了有价值的参考. 关键词： 应变硅 准二维表面势 栅隧穿电流 预测模型     

Investigation of gate oxide traps effect on NAND flash memory by TCAD simulation

The effects of gate oxide traps on gate leakage current and device performance of metal–oxide–nitride–oxide–silicon(MONOS)-structured NAND flash memory are investigated through Sentaurus TCAD. The trap-assisted tunneling(TAT)model is implemented to simulate the leakage current of MONOS-structured memory cell. In this study, trap position, trap density, and trap energy are systematically analyzed for ascertaining their influences on gate leakage current, program/erase speed, and data retention properties. The results show that the traps in blocking layer significantly enhance the gate leakage current and also facilitates the cell program/erase. Trap density ~10¹⁸ cm^-3 and trap energy ~ 1 eV in blocking layer can considerably improve cell program/erase speed without deteriorating data retention. The result conduces to understanding the role of gate oxide traps in cell degradation of MONOS-structured NAND flash memory.     

Dark currents in bulk heterojunction devices for imaging applications: The effect of a cathode interfacial layer

While sol–gel-processed metal oxides are widely used as an electron transport layer to enhance photovoltaic performances, their effect on photodetector application was not studied. We found sol–gel-processed titanium oxide deteriorated dark current characteristics in reverse biases by almost two orders of magnitude, whereas bare Al cathodes exhibited ideal dark current characteristics. Increased dark current came from space charge limited currents in microscopic p-i-p metal-semiconductor-metal configurations. The spatial variation of workfunction values was believed to form local leakage paths by partial filling of traps on the surface of sol–gel titanium oxide.     

0.18 μm MOSFET器件的总剂量辐照效应

对0.18 μm metal-oxide-semiconductor field-effect-transistor (MOSFET)器件进行γ射线辐照实验,讨论分析器件辐照前后关态漏电流、阈值电压、跨导、栅电流、亚阈值斜率等特性参数的变化,研究深亚微米器件的总剂量效应. 通过在隔离氧化物中引入等效陷阱电荷,三维模拟结果与实验结果符合很好. 深亚微米器件栅氧化层对总剂量辐照不敏感,浅沟槽隔离氧化物是导致器件性能退化的主要因素. 关键词： 总剂量效应 浅沟槽隔离 氧化层陷阱正电荷 MOSFET     

应力导致的薄栅氧化层漏电流瞬态特性研究

分别研究了FN隧穿应力和热空穴(HH)应力导致的薄栅氧化层漏电流瞬态特性.在这两种应力条件下,应力导致的漏电流(SILC)与时间的关系均服从幂函数关系,但是二者的幂指数不同.热空穴应力导致的漏电流中,幂指数明显偏离-1,热空穴应力导致的漏电流具有更加显著的瞬态特性.研究结果表明:热空穴SILC机制是由于氧化层空穴的退陷阱效应和正电荷辅助遂穿中心的湮没.利用热电子注入技术,正电荷辅助隧穿电流可被大大地减弱.     

Stress-induced leakage current characteristics of PMOS fabricated by a new multi-deposition multi-annealing technique with full gate last process

In the process of high-k films fabrication, a novel multi deposition multi annealing(MDMA) technique is introduced to replace simple post deposition annealing. The leakage current decreases with the increase of the post deposition annealing(PDA) times. The equivalent oxide thickness(EOT) decreases when the annealing time(s) change from 1 to 2. Furthermore,the characteristics of SILC(stress-induced leakage current) for an ultra-thin SiO_2/HfO_2 gate dielectric stack are studied systematically. The increase of the PDA time(s) from 1 to 2 can decrease the defect and defect generation rate in the HK layer. However, increasing the PDA times to 4 and 7 may introduce too much oxygen, therefore the type of oxygen vacancy changes.     

The conduction mechanism of stress induced leakage current through ultra-thin gate oxide under constant voltage stresses

The conduction mechanism of stress induced leakage current （SILC） through 2nm gate oxide is studied over a gate voltage range between 1.7V and stress voltage under constant voltage stress （CVS）. The simulation results show that the SILC is formed by trap-assisted tunnelling （TAT） process which is dominated by oxide traps induced by high field stresses. Their energy levels obtained by this work are approximately 1.9eV from the oxide conduction band, and the traps are believed to be the oxygen-related donor-like defects induced by high field stresses. The dependence of the trap density on stress time and oxide electric field is also investigated.     

闪速存储器中应力诱生漏电流的产生机理

通过实验研究了闪速存储器存储单元中应力诱生漏电流(SILC)的产生机理. 研究结果表明，在低电场应力下，其可靠性问题主要是由载流子在氧化层里充放电引起，而在高电场下，陷阱和正电荷辅助的隧穿效应导致浮栅电荷变化是引起闪速存储器失效的主要原因. 分别计算了高场应力和低场应力两种情况下SILC中的稳态电流和瞬态电流的大小. 关键词： 闪速存储器 应力诱生漏电流 电容耦合效应 可靠性