单轴晶体包层光纤Bragg光栅反射谱特性模拟研究

本文推导了包层为单轴各向异性晶体的光纤理想正规模特征方程, 应用中值定理, 结合Matlab的数值求解, 提出了这一超越方程的一种求解算法, 并在此基础上, 对包层为单轴各向异性材料的光纤Bragg光栅的反射谱与包层折射率关系进行了模拟分析. 模拟结果表明, k_cl 对反射谱有很大的影响, 不同的k_cl 可以导致不同的光栅反射率和Bragg波长.     

基于等离子体增强化学气相沉积技术的光电子器件多层抗反膜的设计和制作

针对光电子器件端面抗反镀膜的要求,研究了基于等离子体增强化学气相沉积(PECVD)技术的多层抗反膜的设计和制作.首先,对影响SiN_x折射率的因素进行了实验研究,确定了具有大折射率差的SiO₂/SiN_x材料的PECVD沉积条件.根据理论计算分析,设计了四层SiO₂/SiN_x抗反膜结构,能够在70 nm的波长范围内实现低于10^-4的反射率     

带栅极纳米线冷阴极的场增强因子研究

场增强因子是体现场发射冷阴极器件性能优劣的重要参数.利用静电场理论给出了一种带栅极(normal-gated)纳米线冷阴极的场增强因子表示式β=k₁{N²·(L-d₁)²+［1/k₁+(L-d₁)］²}^1/2，且进一步分析了几何参数对场增强因子的影响.结果表明，纳米线突出栅孔的部分(L-d₁)与栅孔半径越大，则场增强因子越大；而纳米线半径越小，则场增强因子越大；当L远大于d₁时满足β∝L/r₀.其中N=N₁(k₁r₀)/N₀(k₁r₀)，N₀(k₁r₀)和N₁(k₁r₀)分别代表零阶和一阶Neumann函数，k₁=0.8936/R，R为栅孔半径，L为纳米线长度，r₀为纳米线半径，d₁表示阴极与栅极间距.     

SiO2分子的基态(X1A1)结构与分析势能函数

应用群论及原子分子反应静力学方法推导了SiO₂分子的电子态及其离解极限，采用B3P86方法，在6-311G^**水平上,优化出SiO₂基态分子稳定构型为单重态的C_2V构型，其平衡核间距R_e=R_Si—O=0.1587 nm,∠OSiO＝111.2°,能量为-440.4392 a.u..同时计算出基态的简正振动频率:对称伸缩振动频率ν(B₂)=945.4cm^-1，弯曲振动频率ν(A₁)=273.5 cm^-1和反对称伸缩振动频率ν(A₁)=1362.9cm^-1.在此基础上，使用多体项展式理论方法，导出了基态SiO₂分子的全空间解析势能函数，该势能函数准确再现了SiO₂(C_2V)平衡结构.     

溶胶凝胶法制备PMMA/SiO2杂化材料

 针对目前PMMA/SiO₂杂化材料制备过程中容易出现的相分离问题，采用原位聚合和同步溶胶凝胶过程制备了聚合物链段与无机组分间有化学键作用的PMMA/SiO₂杂化材料，并应用透射电子显微镜、红外光谱分析仪、X射线衍射分析仪、热失重分析仪等对不同SiO₂含量的PMMA/SiO₂杂化材料的形貌及结构进行了研究。结果表明：SiO₂含量在20%～60%间的PMMA/SiO₂杂化体系没有明显的相分离现象，SiO₂含量在20%～40%间的杂化体系的透光性较好。     

含特异材料光子晶体隧穿模的偏振特性

构造了由普通材料A(SiO₂)和电单负材料B组成的(AB)^N(BA)^N型一维光子晶体.数值计算表明原禁带的1907.3 nm处出现了一个十分尖锐的隧穿模. 入射角增加,该隧穿模的透射率和半峰全宽度均保持不变,但位置发生蓝移, 入射角在15°-65°的区间内,移动率的绝对值 |dλ/dθ| 较大.当B介质的磁导率μ_B 从5增加到10时,只是隧穿模的位置发生了红移. 介质的几何厚度增加时,隧穿模的透射率不变,但其位置红移明显,半峰全宽略有增加.     

基于交通流量的病毒扩散动力学研究

不同于经典扩散模型中节点传染力等同于节点度k的假定, 基于交通流量的病毒扩散模型中, 各个节点的传染力可以等同于节点实际介数b_k. 利用平均场近似方法, 提出基于交通流量SIS病毒修正扩散模型. 根据修正SIS模型, 以最小搜索信息路由为例, 重新研究病毒传播率β, 平均发包率λ同传播阈值β_c, 平稳状态病毒密度ρ之间的关系. 理论分析与实验结果均表明, 当网络拓扑和路由策略一定时, 传播阈值β_c为实际介数b_k的均值<b_k>与其平方的均值<b_k²>的比值. 而稳定状态时感染密度ρ同感染同病毒传播率β, 平均发包率λ 以及λ =1时节点实际介数的均值<b_λ=1> 的乘积倒数存在幂率关系.     

Mg2+掺杂Zn2SiO4:Mn2+的溶胶-凝胶法合成及真空紫外发光特性研究

采用溶胶-凝胶法（sol-gel method）于不同气氛条件下成功合成了Zn_1.92-xMg_xSiO₄:0.08Mn²⁺（0≤x≤0.12）系列粉末样品.利用X射线衍射(XRD)、光致发光(PL)谱等分析手段对Zn_1.92-xMg_xSiO₄:0.08Mn²⁺系列     

应变Ge/Si1-xGex 价带色散模型

基于k·p微扰理论, 通过引入应变哈密顿量作为微扰, 建立了双轴应变Ge/Si_1-xGe_x价带色散关系模型. 模型适于任意晶向弛豫Si_1-xGe_x虚衬底上的应变Ge价带结构, 通过该模型可获得任意k方向应变Ge的价带结构和空穴有效质量. 模型的Matlab模拟结果显示, 应变Ge/Si_1-xGe_x价带带边空穴有效质量随Ge组分的增加而减小, 其各向异性比弛豫Ge更加显著. 本文研究成果对Si基应变Ge MOS器件及集成电路的沟道应力与晶向的设计有参考价值.     

栅漏间表面外延层对4H-SiC功率MESFET击穿 特性的改善机理与结构优化

本文提出了一种带栅漏间表面p型外延层的新型MESFET结构并整合了能精确描述4H-SiC MESFET工作机理的数值模型,模型综合考虑了高场载流子饱和、雪崩碰撞离化以及电场调制等效应. 利用所建模型分析了表面外延层对器件沟道表面电场分布的改善作用,并采用突变结近似法对p型外延层参数与器件输出电流(I_ds)和击穿电压(V_B)的关系进行了研究.结果表明,通过在常规MESFET漏端处引入新的电场峰来降低栅极边缘的强电场峰并在栅漏之间的沟道表面引入p-n结内建电场进一步降低电场峰值,改善了表面电场沿电流方向的分布.通过与常规结构以及场板结构SiC MESFET的特性对比表明,本文提出的结构可以明显改善SiC MESFET的功率特性.此外,针对文中给定的器件结构,获得了优化的设计方案,选择p型外延层厚度为0.12 μupm,掺杂浓度为5× 10¹⁵ cm^-3,可使器件的V_B提高33%而保持I_ds基本不变.     

稀土元素掺杂的Hf基栅介质材料研究进展

随着金属氧化物半导体场效应管(MOSFETs)等比缩小到45 nm技术节点,具有高介电常数的栅介质材料(高k材料)取代传统的SiO₂已经成为必然,然而Hf基高k材料在实际应用中仍然存在许多不足,而稀土元素掺杂在提高Hf基栅介质材料的k值、降低缺陷密度、调整MOSFETs器件的阈值电压等方面表现出明显的优势.本文综述了Hf基高k材料的发展历程,面临的挑战,稀土掺杂对Hf基高k材料性能的调节以及未来研究的趋势. 关键词： k栅介质')" href="#">Hf基高k栅介质 稀土掺杂 氧空位缺陷 有效功函数     

Fabrication and electrical characterization of a MOS memory device containing self-assembled metallic nanoparticles

Floating gate devices with nanoparticles embedded in dielectrics have recently attracted much attention due to the fact that these devices operate as non-volatile memories with high speed, high density and low power consumption. In this paper, memory devices containing gold (Au) nanoparticles have been fabricated using e-gun evaporation. The Au nanoparticles are deposited on a very thin SiO₂ layer and are then fully covered by a HfO₂ layer. The HfO₂ is a high-k dielectric and gives good scalability to the fabricated devices. We studied the effect of the deposition parameters to the size and the shape of the Au nanoparticles using capacitance–voltage and conductance–voltage measurements, we demonstrated that the fabricated device can indeed operate as a low-voltage memory device.     

Growth and interfacial properties of atomic layer deposited Al0.7Ti0.3O y high-k dielectric on Ge substrate

Growth and interfacial properties of atomic layer deposited Al_0.7Ti_0.3O _y on Ge have been investigated as a potential high-k gate dielectric for future Ge-based metal oxide semiconductor devices. A sandwich structure of Al₂O₃/TiO₂ stack is proposed for Al₂O₃/TiO₂ intermixing and high-k/Ge interfacial passivation. The film thicknesses and interface microstructure are characterized by spectroscopy ellipsometry and high-resolution transmission electron microscopy. X-ray photoelectron spectrometry is used to analyze the chemical composition and bonding states, and to reveal the band alignment of high-k/Ge heterojunctions. Metal-oxide-capacitors are formed by depositing aluminum electrodes to perform capacitance–voltage measurements for electrical characteristics. All evidences show a positive prospect of employing atomic layer deposited Al_0.7Ti_0.3O _y as high-k gate dielectric for future Ge-based devices.     

Structural optimization of HfTiSiO high-k gate dielectrics by utilizing in-situ PVD-based fabrication method

We investigated the optimum structure for Ti-containing Hf-based high-k gate dielectrics to achieve EOT scaling below 1 nm. TiO₂/HfSiO/SiO₂ trilayer and HfTiSiO/SiO₂ bilayer structures were fabricated by a newly developed in-situ PVD-based method. We found that thermal diffusion of Ti atoms to SiO₂ underlayers degrades the EOT-J_g characteristics. Our results clearly demonstrated the impact of the trilayered structure with TiO₂ capping for improving EOT-J_g characteristics of the gate stack. We achieved an EOT scaling of 0.78 nm as well as reduced gate leakage of 7.2 × 10⁻² A/cm² for a TiO₂/HfSiO/SiO₂ trilayered high-k dielectric while maintaining the electrical properties at the bottom interface.     

Soft X-ray photoemission study of nitrogen diffusion in TiN/HfO:N gate stacks

The impact of HfO:N post nitridation anneal (PNA) and gate fabrication on the physico-chemical properties of the TiN/HfO:N/SiO₂/Si stack are investigated using Soft X-ray Photoelectron Spectroscopy (S-XPS) and Vacuum UltraViolet Spectroscopic Ellipsometry (VUV-SE). Defects created in the high-k during plasma nitridation are passivated by PNA under O₂. Both oxygen and nitrogen diffusion is observed towards the bottom SiO₂/Si interface together with a regrowth of the SiO₂. These defects play a major role regarding nitrogen diffusion during gate fabrication. Without PNA, no diffusion is observed because O and N atoms are trapped inside the high-k. With PNA and simultaneous defects passivation, nitrogen from both metal gate and high-k diffuses towards the bottom SiO₂/Si interface.     

高k栅介质对肖特基源漏超薄体SOI MOSFET性能的影响

研究了高k栅介质对肖特基源漏超薄体SOI MOSFET性能的影响.随着栅介质介电常数增大，肖特基源漏(SBSD) SOI MOSFET的开态电流减小，这表明边缘感应势垒降低效应(FIBL)并不是对势垒产生影响的主要机理.源端附近边缘感应势垒屏蔽效应(FIBS)是SBSD SOI MOSFET开态电流减小的主要原因.同时还发现，源漏与栅是否对准，高k栅介质对器件性能的影响也不相同.如果源漏与栅交叠，高k栅介质与硅衬底之间加入过渡层可以有效地抑制FIBS效应.如果源漏偏离栅，采用高k侧墙并结合堆叠栅结构，可以提高驱动电流.分析结果表明，来自栅极的电力线在介电常数不同的材料界面发生两次折射.根据结构参数的不同可以调节电力线的疏密，从而达到改变势垒高度，调节驱动电流的目的. 关键词： k栅介质')" href="#">高k栅介质 肖特基源漏(SBSD) 边缘感应势垒屏蔽(FIBS) 绝缘衬底上的硅(SOI)     

Stability and band offsets between Si and LaAlO<Subscript>3</Subscript>

The replacement of traditional SiO₂ with high-k oxides allows the physical thickness of the gate dielectric to be thinner without the tunneling problem in Si-based metal-oxide-semiconductor field-effect transistors. LaAlO₃ appears to be a promising high-k material for use in future ultra large scale integrated devices. In the present paper, the electronic properties of Si/LaAlO₃ (001) heterojunctions are investigated by first-principles calculations. We studied the initial adsorption of Si atoms on the LaAlO₃ (001) surface, and found that Si atoms preferentially adsorb on top of oxygen atoms at higher coverage. The surface phase diagrams indicate that Si atoms may substitute oxygen atoms at the LaO-terminated surface. The band offsets, electronic density of states, and atomic charges are analyzed for the various Si/LaAlO₃ heterojunctions. Our results suggest that the Si/AlO₂ interface is suitable for the design of metal oxide semiconductor devices because the valence and conduction band offsets are both larger than 1 eV.     

高k栅介质应变Si SOI MOSFET的阈值电压解析模型

在结合应变Si,高k栅和SOI结构三者的优点的基础上,提出了一种新型的高k栅介质应变Si全耗尽SOI MOSFET结构.通过求解二维泊松方程建立了该新结构的二维阈值电压模型,在该模型中考虑了影响阈值电压的主要参数.分析了阈值电压与弛豫层中的Ge组分、应变Si层厚度的关系.研究结果表明阈值电压随弛豫层中Ge组分的提高和应变Si层的厚度增加而降低.此外,还分析了阈值电压与高k栅介质的介电常数和应变Si层的掺杂浓度的关系.研究结果表明阈值电压随高k介质的介 关键词： 应变Si k栅')" href="#">高k栅 短沟道效应 漏致势垒降低     

Polymer thin-film transistors with high dielectric constant gate insulators

Field-effect transistors consisting of poly(3-hexylthiophene) have been fabricated with high dielectric constant SrBi₂Ta₂O₉ films working as the gate insulator. Significantly enhanced gate effects were observed in these devices compared to similar transistors with conventional SiO₂ gate dielectric. Our devices exhibited operating voltages around 10 V, as compared to about 100 V for devices employing SiO₂ as the gate dielectric. Moreover, inverters based on such polymer transistors were demonstrated with nice input–output characteristics. PACS 82.35.Cd