Synergistic effects of total ionizing dose on single event upset sensitivity in static random access memory under proton irradiation

Nitrogen plasma passivation （NPP） on （111） germanium （Ge） was studied in terms of the interface trap density, roughness, and interfacial layer thickness using plasma-enhanced chemical vapor deposition （PECVD）. The results show that NPP not only reduces the interface states, but also improves the surface roughness of Ge, which is beneficial for suppressing the channel scattering at both low and high field regions of Ge MOSFETs. However, the interracial layer thickness is also increased by the NPP treatment, which will impact the equivalent oxide thickness （EOT） scaling and thus degrade the device performance gain from the improvement of the surface morphology and the interface passivation. To obtain better device performance of Ge MOSFETs, suppressing the interfacial layer regrowth as well as a trade-off with reducing the interface states and roughness should be considered carefully when using the NPP process.     

A Closed-Form Model for Position-Dependent Potential across the Channel in DG-MOSFETs

A closed-form model for electrostatic potential distribution in the direction normal to the channel for double-gate （DG） MOSFETs is presented. The effects of doping （NA for nMOS） and minority carriers both are taken into account for the first time, in solving Poisson＇s equation analytically. Excellent agreement between model-predicted results and numerical device simulation is achieved for a wide range of body thickness, light or high channeldoping, under various bias conditions. This complete closed form for position-dependent potential distribution has wide applications for MOS compact modelling and device design.     

Electron Backscattered Diffraction of Transgranular Crack Propagation in Soft Steel

We consider the crack propagation in a soft steel sheet during the formation. The drawability is considered in relation with the structural anisotropy, the mechanical behaviour is related to both the grain morphology and the texture. The structure heterogeneity could lead to the apparition of micro-cracks. The results show the texture effect on the crack propagation and on the crack arrest in soft steel during the formation. The EBSD technique allows to show that the adjustment of the grain orientation from the initial main component {111}（112） towards the deformation orientation {111}（110） incites a trans-granular crack through a grain with initial {111}（112） orientation in a globally ductile material. It is the presence of grains with {111}（110） orientation which permits the closing of micro-cracks.     

Schottky Barrier Formation at a Carbon Nanotube-Scandium Junction

Recent experiment shows that scandium （Sc） can make a good performance contact with carbon nanotubes （CNTs） to fabricate n-type field effect transistor （n-FET）. We study the Schottky barrier （SB） of scandium （Sc） and palladium （Pd） with a （8,0） single-wall CNT （SWCNT） using first-principles calculation. It is found that the p-type SB height （SBH） of the Pd-CNT contact is about 0.34 eV, which is in good agreement with the experimental data. For the Sc-CNT contact, an n-type contact is formed and the SBH is about O.08eV in agreement with the experimental observations. Our calculation demonstrates that by contacting CNT with Pd and Sc, p-FET and n-FET can be fabricated, respectively. The dipole effect at the interface is used to explain our result.     

High-mobility germanium p-MOSFETs by using HCI and （NH4）2S surface passivation

To achieve a high-quality high-κ/Ge interfaces for high hole mobility Ge p-MOSFET applications, a simple chemical cleaning and surface passivation scheme is introduced, and Ge p-MOSFETs with effective channel hole mobility up to 665 cm2/V.s are demonstrated on a Ge （111） substrate. Moreover, a physical model is proposed to explain the dipole layer formation at the metal-oxide-semiconductor （MOS） interface by analyzing the electrical characteristics of HCl- and （NH4）2S-passivated samples.     

Temperature-driven spin reorientation transitionof magnetron sputtered nickel thin film

The temperature-driven spin reorientation transition of magnetron sputtered Ni/Si （111） systems has been studied. The relationship between ac initial susceptibility and temperature of nickel films with different thicknesses shows that the magnetization orientation changes from in-plane to out-of-plane with the increase of temperature. The temperature dependence of mugnetoelastic, magneto-crystalline, and magnetostatic anisotropies determines the direction of the reorientation transition. The temperature-driven spin reorientation transition is supported by Hall coefficient measurements which show that its temperature dependence is similar to that of susceptibility.     

Distribution Function of Mesoscopic Hopping Conductance

We study mesoscopic hopping conductance by computer simulation distribution functions(DFs),It is found that the distributions obtained by choosing randomly the chemical potentials(for a fixed impurity configuration),which corresponds to a typical experimental situation,coincide with those obtained when both impurity configuration and chemical potential are chosen randmly,in agreement with the ergodicity hypothesis.The DFs in shape obtained for one-dimensional system are found to be quite close to the predictions of the theory by Raikh and Ruzin.For the two-dimensional case,the DFs both for a narrow system and thin film look to be similar(and close to the one-dimensional case).The DF for the conductance of the square sample is nearly Gaussian.     

Effect of CO2 Addition on Preparation of Diamond Films by Direct-Current Hot-Cathode Plasma Chemical Vapor Deposition Method

Diamond films are deposited on Mo substrates by dc hot-cathode plasma chemical vapor deposition method using a CH4-H2-CO2 gas mixture. Adjusting the flow of CO2, we study the relevant influence on surface morphology, grain orientation and crystalline quality of films with scanning electron microscopy, x-ray diffraction, Raman spectroscopy, respectively. The results show that grain orientation of the films has a transition with the increasing CO2 addition, from （100） orientation to （110） orientation and then （111） orientation. The crystalline quality is improved but the growth rate is decreased by raising the flow of CO2. The experimental results are also discussed briefly.     

Dependence of short channel length on negative/positive bias temperature instability (NBTI/PBTI) for 3D FinFET devices

A comprehensive study of the negative and positive bias temperature instability(NBTI/PBTI)of 3D FinFET devices with different small channel lengths is presented.It is found while with the channel lengths shrinking from 100 nm to 30 nm,both the NBTI characteristics of p-FinFET and PBTI characteristics of n-FinFET turn better.Moreover,the channel length dependence on NBTI is more serious than that on PBTI.Through the analysis of the physical mechanism of BTI and the simulation of 3-D stress in the FinFET device,a physical mechanism of the channel length dependence on NBTI/PBTI is proposed.Both extra fluorine passivation in the corner of bulk oxide and stronger channel stress in p-FinFETs with shorter channel length causes less NBTI issue,while the extra nitrogen passivation in the corner of bulk oxide induces less PBTI degradation as the channel length decreasing for n-FinFETs.The mechanism well matches the experimental result and provides one helpful guide for the improvement of reliability issues in the advanced FinFET process.     

Mobility Enhancement and Gate-Induced-Drain-Leakage Analysis of Strained-SiGe Channel p-MOSFETs with Higher-k LaLuO3 Gate Dielectric

A strained-SiGe p-channel metal-oxide-semiconductor-field-effect transistors （p-MOSFETS） with higher-k LaLu03 gate dielectric was fabricated and electrically characterized. The novel higher-k （k-30） gate dielectric, LaLuO3, was deposited by molecular-beam deposition and shows good quality for integration into the transistor. The transistor features good output and transfer characteristics. The hole mobility was extracted by the splitting C-V method and a value of 2OOcm2/V.s was obtained for strong inversion conditions, which indicates that the hole mobility is well enhanced by SiGe channel and that the LaLuO3 layer does not induce additional significant carrier scattering. Gate induced drain leakage is measured and analyzed by using an analytical model. Band-to- band tunneling et~ciencies under high and low fields are found to be different, and the tunneling mechanism is discussed.     

Performance of La203/InA1N/GaN metal-oxide-semiconductor high electron mobility transistors

We report on the performance of La203/InA1N/GaN metal-oxide-semiconductor high electron mobility transistors （MOSHEMTs） and InA1N/GaN high electron mobility transistors （HEMTs）. The MOSHEMT presents a maximum drain current of 961 mA/mm at Vgs = 4 V and a maximum transconductance of 130 mS/mm compared with 710 mA/mm at Vgs = 1 V and 131 mS/mm for the HEMT device, while the gate leakage current in the reverse direction could be reduced by four orders of magnitude. Compared with the HEMT device of a similar geometry, MOSHEMT presents a large gate voltage swing and negligible current collapse.     

Influence of the channel electric field distribution on the polarization Coulomb field scattering in In0.18Al0.82N/AIN/GaN heterostructure field-effect transistors

By making use of the quasi-two-dimensional （quasi-2D） model, the current-voltage （l-V） characteristics of In0AsA10.82N/A1N/GaN heterostructure field-effect transistors （HFETs） with different gate lengths are simulated based on the measured capacitance-voltage （C-V） characteristics and I-V characteristics. By analyzing the variation of the electron mobility for the two-dimensional electron gas （2DEG） with electric field, it is found that the different polarization charge distributions generated by the different channel electric field distributions can result in different polarization Coulomb field scatterings. The difference between the electron mobilities primarily caused by the polarization Coulomb field scatterings can reach up to 1522.9 cm2/V.s for the prepared In0.38AI0.82N/A1N/GaN HFETs. In addition, when the 2DEG sheet density is modulated by the drain-source bias, the electron mobility presents a peak with the variation of the 2DEG sheet density, the gate length is smaller, and the 2DEG sheet density corresponding to the peak point is higher.     

Improved interface properties of an Hf02 gate dielectric GaAs MOS device by using SiNx as an interfacial passivation layer

A GaAs metal-oxide-semiconductor （MOS） capacitor with HfO2 as gate dielectric and silicon nitride （SiNx） as the interlayer （IL） is fabricated. Experimental results show that the sample with the SiNx IL has an improved capacitance- voltage characteristic, lower leakage current density （0.785 × 10^-6 Alcm^2 at Vfo ＋ 1 V） and lower interface-state density （2.9 × 10^12 eV^-1 ·cm^-2） compared with other samples with N2- or NH3-plasma pretreatment. The influences of post- deposition annealing temperature on electrical properties are also investigated for the samples with SiNx IL. The sample annealed at 600 ℃ exhibits better electrical properties than that annealed at 500 ℃, which is attributed to the suppression of native oxides, as confirmed by XPS analyses.     

Design consideration and fabrication of 1.2-kV 4H-SiC trenched-and-implanted vertical junction field-effect transistors

We present the design consideration and fabrication of 4H-SiC trenched-and-implanted vertical junction field-effect transistors （TI-VJFETs）. Different design factors, including channel width, channel doping, and mesa height, are con- sidered and evaluated by numerical simulations. Based on the simulation result, normally-on and normally-off devices are fabricated. The fabricated device has a 12 μm thick drift layer with 8 × 10^15 cm^-3 N-type doping and 2.6 μm channel length. The normally-on device shows a 1.2 kV blocking capability with a minimum on-state resistance of 2.33 mΩ.cm2, while the normally-off device shows an on-state resistance of 3.85 mΩ.cm2. Both the on-state and the blocking performances of the device are close to the state-of-the-art values in this voltage range.     

A voltage-controlled chaotic oscillator based on carbon nanotube field-effect transistor for low-power embedded systems

This paper presents a compact and low-power-based discrete-time chaotic oscillator based on a carbon nanotube field-effect transistor implemented using Wong and Deng＇s well-known model. The chaotic circuit is composed of a nonlinear circuit that creates an adjustable chaos map, two sample and hold cells for capture and delay functions, and a voltage shifter that works as a buffer and adjusts the output voltage for feedback. The operation of the chaotic circuit is verified with the SPICE software package, which uses a supply voltage of 0.9 V at a frequency of 20 kHz. The time series, frequency spectra, transitions in phase space, sensitivity with the initial condition diagrams, and bifurcation phenomena are presented. The main advantage of this circuit is that its chaotic signal can be generated while dissipating approximately 7.8 μW of power, making it suitable for embedded systems where many chaos-signal generators are required on a single chip.     

Charge transport in monolayer poly（3-hexylthiophene） thin-film transistors

It is found that ultrathin poly（3-hexylthiophene） （P3HT） film with a 2.5 nm-thick layer exhibits a higher mobility of 5.0× 10-2 cm2/V-s than its bulk counterpart. The crystalline structure of the as-fabricated ultrathin P3HT layer is verified by atomic force microscopy as well as grazing incidence X-ray diffraction. Transient measurements of the as-fabricated transistors reveal the influence of the interface traps on charge transport. These results are explained by the trap energy level distribution at the interface manipulated by layers of polymer film.     

A percolation study of RTS noise in deep sub-micron MOSFET by Monte Carlo simulation

Based on percolation theory and random telegraph signal (RTS) noise generation mechanism, a numerical model for RTS in deep submicron metal-oxide-semiconductor field-effect transistor (MOSFET) was presented, with which the dependence of Tc/Te (where Tc=capture time, Te=emission period ) on energy levels and trap depth with respect to the interface of traps can be simulated. Compared with experimental results, the simulated ones showed a good qualitative agreement.     

A two-dimensional threshold voltage analytical model for metal-gate/high-k/SiO₂ /Si stacked MOSFETs

In this paper the influences of the metal-gate and high-k/SiO 2 /Si stacked structure on the metal-oxide-semiconductor field-effect transistor(MOSFET) are investigated.The flat-band voltage is revised by considering the influences of stacked structure and metal-semiconductor work function fluctuation.The two-dimensional Poisson’s equation of potential distribution is presented.A threshold voltage analytical model for metal-gate/high-k/SiO 2 /Si stacked MOSFETs is developed by solving these Poisson’s equations using the boundary conditions.The model is verified by a two-dimensional device simulator,which provides the basic design guidance for metal-gate/high-k/SiO 2 /Si stacked MOSFETs.     

高$lt;i$gt;k$lt;/i$gt;栅介质小尺寸全耗尽绝缘体上锗p型金属氧化物半导体场效应晶体管漏源电流模型

通过求解沟道的二维泊松方程得到沟道表面势和沟道反型层电荷, 建立了高k栅介质小尺寸绝缘体上锗(GeOI) p型金属氧化物半导体场效应晶体管(PMOSFET)的漏源电流解析模型. 模型包括了速度饱和效应、迁移率调制效应和沟长调制效应, 同时考虑了栅氧化层和埋氧层与沟道界面处的界面陷阱电荷、氧化层固定电荷对漏源电流的影响. 在饱和区和非饱和区, 漏源电流模拟结果与实验数据符合得较好, 证实了模型的正确性和实用性. 利用建立的漏源电流模型模拟分析了器件主要结构和物理参数对跨导、漏导、截止频率和电压增益的影响, 对GeOI PMOSFET的设计具有一定的指导作用. 关键词： 绝缘体上锗p型金属氧化物半导体场效应晶体管 漏源电流模型 跨导 截止频率     

Angle-resolved x-ray photoelectron spectroscopy study of GeO_x growth by plasma post-oxidation

The growth process of GeO_x films formed by plasma post-oxidation(PPO) at room temperature(RT) is investigated using angle-resolved x-ray photoelectron spectroscopy(AR-XPS). The experimental results show that the distributions of the Ge~(4+)states, a mixture of the Ge_(2+)and Ge~(3+)states, and the Ge~(1+)states are localized from the GeO_x surface to the GeO_x/Ge interface. Moreover, the Ge~(1+)states are predominant when the two outermost layers of Ge atoms are oxidized.These findings are helpful for establishing in-depth knowledge of the growth mechanism of the GeO_x layer and valuable for the optimization of Ge-based gate stacks for future complementary metal–oxide–semiconductor(MOS) field-effect transistor(CMOSFET) devices.