All-optical prefix tree adder with the help of terahertz optical asymmetric demultiplexer

We propose and describe an all-optical prefix tree adder with the help of a terahertz optical asymmetric demultiplexer (TOAD) using a set of optical switches. The prefix tree adder is useful in compound adder implementation. It is preferred over the ripple carry adder and the carry lookahead adder. We also describe the principle and possibilities of the all-optical prefix tree adder. The theoretical model is presented and verified through numerical simulation. The new method promises higher processing speed and accuracy. The model can be extended for studying more complex all-optical circuits of enhanced functionality in which the prefix tree adder is the basic building block.     

Shannon Logic Based Novel QCA Full Adder Design with Energy Dissipation Analysis

Quantum-dot Cellular Automata (QCA) is an emerging nanotechnology to replace VLSI-CMOS digital circuits. Due to its attractive features such as low power consumption, ultra-high speed switching, high device density, several digital arithmetic circuits have been proposed. Adder circuit is the most prominent component used for arithmetic operations. All other arithmetic operation can be successively performed using adder circuits. This paper presents Shannon logic based QCA efficient full adder circuit for arithmetic operations. Shannon logic expression with control variables helps the designer to reduce hardware cost; using with minimum foot prints of the chip size. The mathematical models of the proposed adder are verified with the theoretical values. In addition, the energy dissipation losses of the proposed adder are carried out. The energy dissipation calculation is evaluated under the three separate tunneling energy levels, at temperature T = 2K.The proposed adder dissipates less power. QCAPro tool is used for estimating the energy dissipation. In this paper we proposed novel Shannon based adder for arithmetic calculations. This adder has been verified in different aspects like using Boolean algebra besides it power analysis has been calculated. In addition 1-bit full adder has been enhanced to propose 2-bit and 4-bit adder circuits.     

Implementation of parallel adder using combinatorial logic architecture

The algorithm and optical implementation of full parallel adder using combina-torial logic architecture have been suggested in this paper.The hybrid full parallel adder,which can perform multiple bits addition simultaneously,is implemented by utilizing VLSItechnology and acoustooptic Bragg cells.The algorithm has the advantages of high parallelismand easy optical implementation.The full parallel adder finishes n-bit addition within the du-ration T_d if the pipeline architecture is employed,whose hardware complexity is O(n~2).     

感应叠加过程行波分析和模拟

 采用变换矩阵为研究工具对感应叠加过程中行波的传播、透射、反射进行了分析，得到了和集中参数分析一致的稳定解，给出了电压随时间变化的细节。建立了3.5 MeV注入器脉冲功率源和感应叠加结构的电路模型，得到的感应腔压模拟波形和实验波形基本一致，结合行波分析法基本解释了腔压波形和Blumlein线输出波形之间较大差异的成因，阴极叠加电压的模拟也反映了实验中主脉冲后的反射波形。     

Robust Coplanar Full Adder Based on Novel Inverter in Quantum Cellular Automata

Quantum dot cellular automata (QCA) is one of the nano-scale computing paradigms which promises high speed and ultra-low power consumption. Since the one-bit full adder is a fundamental building block of arithmetic circuits, designing an efficient QCA full adder cell is very imperative in this new technology. In this paper, we propose a QCA full adder using a new inverter gate which leads to reduced complexity and area occupation. The proposed layout is simulated by the QCA designer engines. We also provide a performance comparison of our proposed QCA full adder with the previous relevant designs. Furthermore, a detailed analysis of energy dissipation is performed which demonstrates the superiority of the proposed design in terms of the energy efficiency.

     

基于混沌计算的全加器实现

混沌计算是一种使用混沌单元实现基本逻辑门的新计算模式. 基于混沌计算的思想提出了实现全加器的新方法,通过设定不同的阀值及判断条件,使用一个混沌单元实现全加器. 与传统全加器的实现相比,降低了全加器结构上的复杂性,提供了实现上的灵活性. 最后,以Logistic映射为例给出了使用一个混沌单元实现全加器的方法. 关键词： 混沌 混沌计算 全加器     

Quantum legitimacy of reversible gate and a new design of multiplier based on R gate

Quantum full adders play a key role in the design of quantum computers. The efficiency of a quantum adder directly determines the speed of the quantum computer, and its complexity is closely related to the difficulty and the cost of building a quantum computer. The existed full adder based on R gate is a great design but it is not suitable to construct a quantum multiplier. We show the quantum legitimacy of some common reversible gates, then use R gate to propose a new design of a quantum full adder. We utilize the new designed quantum full adder to optimize the quantum multiplier which is based on R gate. It is shown that the new designed one can be optimized by a local optimization rule so that it will have lower quantum cost than before.     

Optical Module for Modified Signed-Digit Computing Based on Bit Plane Encoding and Pattern Operations

We propose here a new optical modified signed-digit (MSD) adder module based on bit plane pattern encoding of MSD digits and pattern operations. The pattern operations required in the algorithm are duplication, combination and shifting. They are simply performed by using optical components such as beam splitters, mirrors and parallel plates, instead of optical logic arrays. An optical MSD adder module comprised of six properly interacting blocks with all optical components packaged on a common substrate is presented in detail. We analyze the system errors caused by manufacture and alignment of optical components, the information throughput, the intensity nonuniformity and the system volume of the adder module.     

All-optical carry lookahead adder with the help of terahertz optical asymmetric demultiplexer

An all-optical model of carry lookahead adder (CLA) implemented with a semiconductor optical amplifier (SOA)-assisted Sagnac interferometer (TOAD) is presented. The model accounts for the SOA small signal gain, linewidth enhancement factor, the switching pulses energy and width and the Sagnac loop asymmetry. Adder is a very basic component in a central processing unit. The CLA is the highest speed adder nowadays. Theoritical model is presented and verified through numerical simulation. The method promises both higher processing speed and accuracy. The model can be enhanced the functionality in which carry lookahead adder is the basic building block.     

Balanced biosynthesis and trigger threshold resulting in a double adder mechanism of cell size control

How cells accomplish cell size homeostasis is a fascinating topic, and several cell size regulation mechanisms were proposed: timer, sizer, and adder. Recently the adder model has received a great deal of attention. Adder property was also found in the DNA replication cycle. This paper aims to explain the adder phenomenon both in the division-centric picture and replication-centric picture at the molecular level. We established a self-replication model, and the system reached a steady state quickly based on evolution rules. We collected tens of thousands of cells in the same trajectory and calculated the Pearson correlation coefficient between biological variables to decide which regulatory mechanism was adopted by cells. Our simulation results confirmed the double-adder mechanism. Chromosome replication initiation and cell division control are independent and regulated by respective proteins.Cell size homeostasis originates from division control and has nothing to do with replication initiation control. At a slow growth rate, the deviation from adder toward sizer comes from a significant division protein degradation rate when division protein is auto-inhibited. Our results indicated the two necessary conditions in the double-adder mechanism: one is balanced biosynthesis, and the other is that there is a protein trigger threshold to inspire DNA replication initiation and cell division. Our results give insight to the regulatory mechanism of cell size and instructive to synthetic biology.     

One-step optical negabinary and modified signed-digit adder

A one-step algorithm for parallel negabinary addition of two negabinary numbers is achieved by minimizing the truth-table for the two-step algorithm. Without increasing the encoding cell size or adding complexity of the corresponding optical system, the proposed one-step scheme doubles the computation speed. The optical system can also be used to realize a one-step modified signed digit adder. Additionally, optical implementation of negabinary multiplication using this proposed one-step optical adder is discussed.     

Method of implementation of frequency encoded all optical half adder, half subtractor and full adder based on semiconductor optical amplifiers and add drop multiplexers

A novel frequency encoded all optical half adder, half subtractor and full adder are proposed. The implementation is ultrafast one and the frequency encoding makes it intensity loss dependent problem free. The use of polarization insensitive four-wave mixing makes the design polarization independent and the hardware simple. The frequency conversion by the reflective semiconductor optical amplifiers (RSOA) makes the design faster compared to other semiconductor optical amplifiers (SOA) based design.     

Modular Adder Designs Using Optimal Reversible and Fault Tolerant Gates in Field-Coupled QCA Nanocomputing

The challenges which the CMOS technology is facing toward the end of the technology roadmap calls for an investigation of various logical and technological solutions to CMOS at the nano scale. Two such paradigms which are considered in this paper are the reversible logic and the quantum-dot cellular automata (QCA) nanotechnology. Firstly, a new 3 × 3 reversible and universal gate, RG-QCA, is proposed and implemented in QCA technology using conventional 3-input majority voter based logic. Further the gate is optimized by using explicit interaction of cells and this optimized gate is then used to design an optimized modular full adder in QCA. Another configuration of RG-QCA gate, CRG-QCA, is then proposed which is a 4 × 4 gate and includes the fault tolerant characteristics and parity preserving nature. The proposed CRG-QCA gate is then tested to design a fault tolerant full adder circuit. Extensive comparisons of gate and adder circuits are drawn with the existing literature and it is envisaged that our proposed designs perform better and are cost efficient in QCA technology.     

On Design of Parity Preserving Reversible Adder Circuits

In this paper novel parity preserving reversible logic blocks are presented and verified. Then, we present cost-effective parity preserving reversible implementations of Full Adder, 4:2 Compressor, Binary to BCD converter, and BCD adder using these blocks. The proposed parity preserving reversible BCD adder is designed by cascading the presented 4-digit parity preserving reversible Full Adder and a parity preserving reversible Binary to BCD Converter. In this design, instead of realizing the detection and correction unit, we design a Binary to BCD converter that its inputs are the output of parity preserving binary adder, and its output is a parity preserving BCD digit. In addition, several theorems on the numbers of garbage outputs, constant inputs, quantum cost and delay of the designs have been presented to show its optimality. In the presented circuits, the delay and the quantum cost are reduced by deriving designs based on the proposed parity preserving reversible blocks. The advantages of the proposed designs over the existing ones are quantitatively described and analysed. All the scales are in the Nano-metric area.     

A Power-Efficient Single Layer Full Adder Design in Field-Coupled QCA Nanocomputing

As an emerging technology device, Quantum-dot cellular automata (QCA) may be a suitable substitute for traditional semiconductor transistor technology. Arithmetic logic unit in field-coupled QCA has been also studied extensively in recent year. In this paper, the new low-power Exclusive-OR gate is presented, which is mainly based on QCA cellular leveled format. This Exclusive-OR gate can be used to design various useful QCA circuits. By using this gate, we design and implement a novel full adder circuit with low dissipation. The circuit is designed using only 45 normal cells in a single layer without crossover. Compared with previous designs, both decimal adders achieve better performance in terms of latency and overall cost. The operation of the proposed circuit has been verified by QCADesigner version 2.0.3 and energy dissipation investigated by QCAPro tool. We also compared with previous designs in terms of power dissipation, cell-counts, area, latency and cost. The proposed full adder has the smallest area with less number of cells. And the total energy dissipation of our proposed full adder are only 0.05112 eV, 0.07454 eV and 0.10181 eV when tunneling energy levels are 0.5 Ek, 1 Ek and 1.5 Ek, respectively. The proposed single full adder also has the lowest total energy dissipation with a reduction of 20.94, 11.25 and 4.82% in 0.5 E_k, 1 E_k and 1.5 E_k tunneling energy levels, respectively when compared with the previous most power-efficient design.

     

Adder on ternary base elements for a quantum computer

A circuit consisting of elementary quantum logic operators has been proposed for an adder in the ternary number system. A sequence of RF magnetic field pulses has been found for its implementation by the nuclear magnetic resonance method on a chain of quadrupole nuclei with spin I = 1. The numerical simulation of the adder operation has been performed.     

Optical arithmetic unit using bit-WDM

A novel arithmetic unit is proposed consisting of a pipelined optical ripple carry adder that adds two words with bits multiplexed by different wavelengths on a single fiber. The addition result is returned to a fiber bus in the same format as the incoming words. The corresponding operand bit pairs are split off the fiber using wavelength division demultiplexers. Full adders compute the sum for each bit pair and the carry from the next lower significant bit pair. The full adder uses couplers and NOT, NOR and novel XOR logic gates constructed using semiconductor optical amplifiers for gain and wavelength shifting.     

基于细菌视紫红质膜的全光逻辑门

基于在细菌视紫红质膜中的自衍射，我们提出了全光非、异或、半加器及同或门逻辑操作。利用衍射光与记录光偏振状态之间的关系，我们演示了非门和同或门逻辑操作。 通过衍射光，记录光和读出光之间的偏振状态的关系，我们实现了异或逻辑操作和具有三个输入端的半加器逻辑操作。所用方法简单实用。     

Design of Low-Complexity and High-Speed Coplanar Four-Bit Ripple Carry Adder in QCA Technology

Quantum-dot Cellular Automata (QCA) technology is a suitable technology to replace CMOS technology due to low-power consumption, high-speed and high-density devices. Full adder has an important role in the digital circuit design. This paper presents and evaluates a novel single-layer four-bit QCA Ripple Carry Adder (RCA) circuit. The developed four-bit QCA RCA circuit is based on novel QCA full adder circuit. The developed circuits are simulated using QCADesigner tool version 2.0.3. The simulation results show that the developed circuits have advantages in comparison with existing single-layer and multilayer circuits in terms of cell count, area occupation and circuit latency.     

Quantization effects in first-order digital recursive filters with the representation of numbers in a complement code and rounding off after addition

We study the processes in low-and high-pass filters that use fixed-point arithmetic, assuming that the filter parameter is exactly specified and the multiplication operation is performed, while the addition operation is carried out in a complement code with rounding off. The adder has a sawtooth characteristic. The method of mapping is used for a study of free oscillations and oscillations under constant bias at the input, both in the absence and in the presence of the adder overflow. Expressions for calculation of the most probable modes for an arbitrary number of quantization levels are obtained. __________ Translated from Izvestiya Vysshikh Uchebnykh Zavedenii, Radiofizika, Vol. 48, No. 12, pp. 1067–1076, December 2005.