共查询到18条相似文献,搜索用时 406 毫秒
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为解决传统解码仪存在的体积大、兼容性差等问题,提出利用FPGA实现解调IRIG-B(DC)码信息的电路板卡的设计,该板卡能够解调出IRIG-B(DC)码的时间信息,根据此时间信息,解码卡可以输出相应的秒脉冲,并且通过RS232串口将解调出的时间信息传送给上位机。试验证明该解码卡具有环境适应性强、体积小、结构简明、应用范围广等特点,可以满足实际应用场所对IRIG-B码解码的要求。 相似文献
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AFDX(航空电子全双工切换以太网)作为大型客机和运输机上的主流机载通信网络,其应用越来越广泛,对AFDX网络及设备的测试需求也必将与日俱增;针对这一需求,提出了一种AFDX终端测试技术的实现方法;该方案使用大规模FPGA和高性能嵌入式处理器,实现了一个AFDX终端系统及终端测试功能;应用结果表明其较好地满足了航空电子网络数据传输的实时性和可靠性需求,并能对AFDX网络的功能和主要性能指标进行测试;该测试终端具备最大128个虚拟链路、1~128 ms带宽分配间隙,可进行协议解码分析、故障注入与检测、误码率测试以及IRIG-B时戳等测试功能。 相似文献
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为了提高对时间统一系统IRIG-B码信号的监测效率,需要一套自动监测系统;本文结合某型号时间统一系统,针对该时统设备输出的通用IRIG-B(DC)格式时间码,介绍了一种基于Arduino的便携式IRIG-B(DC)信号监视系统的设计过程,给出了以开放源代码硬件项目平台Arduino为核心构建的“输入控制+逻辑处理+数据处理+数据交互+数据存储+网络传输+实时显示”的系统硬件设计结构;利用Arduino内高度集成的AVR二次编译封装库,将复杂的逻辑控制和数据处理等底层的指令封装成简单实用的函数调用,完成了整个系统的任务调度和管理,实现了对时间统一系统IRIG-B(DC)信号的波形采集、数据分析、时间解调、状态监视、实时显示以及数据存储等功能;测试结果表明,系统设计简洁,工作稳定可靠,设计指标满足功能需求。 相似文献
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针对电脑主机多采用BIOS内时钟而导致系统时间不精确的问题,提出一种基于北斗/GPS芯片的网络授时系统设计。该系统采用可编程逻辑器件(FPGA)作为主控芯片,接收北斗/GPS双模芯片提供的UTC时间码流,解码并通过网口发送到PC机上作为精准时间。同时多个设备间相互连接,实现多设备之间的数据传输,增强系统的稳定性和可靠性。传输速率可达100Mbps。实验证明:北斗/GPS接收信号稳定,传输的时间信息准确,北斗/GPS所解时间信息误差不超过80ns,设备与PC机100Mbps传输速率误差在1-2ms,系统稳定、可靠。 相似文献
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时统系统是各种光电设备、导航系统上必备的高精度电子设备。针对天文导航和惯性导航设备对时统信息的需求,设计了一种多路串行时码输出的时统系统,阐述了设计方案及软硬件实现流程。基于FPGA实现了多路串口通信,可方便扩展更多路串口,通过DSP控制串口工作方式及GPS信息处理,可适用多数GPS接收机,处理系统输出格式。实验证明该设计功能齐全、可靠性高、易于调试,适用于为导航设备提供时间信号和频率信号以实现整个设备的时间和频率统一。 相似文献
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A decoding scheme of the orthogonally concatenated codes with low resource utilizations is proposed. In the optical transport networks (OTN), forward error-correction (FEC) techniques are used to reduce the errors which occur in transmissions. Two-orthogonal-concatenated (TOC) codes are widely used in FEC techniques for their powerful error-correction capabilities based on the iterative decoding procedure. However, the framing structure is complex so the decoding procedure is more difficult than the decoding of in–out concatenated codes. And the powerful error-correction capability relies on the multi-iterative decoding processing, thus how to effectively utilize the hardware resources is a very important problem. Especially when the decoding procedure is implemented in the field programmable gate array (FPGA) devices, effective optimizations are required for the limited resources. In this paper we present an iterative decoding scheme in FPGA with low resource utilizations. As an example, an actual engineering application under the G.975.1 recommendation is given to show the efficiency of the proposed design. 相似文献
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The impact of fiber polarization mode dispersion (PMD) on the bit error rate (BER) performance of a direct sequence optical code-division multiple-access system is analyzed by the split-step Fourier method based on the coupled nonlinear Schrödinger equation, the three-dimensional Poincare sphere theory and the Jones matrix method. When the incident pulse's width is bigness than the chip duration, which causes spreading and overlapping of chips and degrades system performance due to increased interchip interference and reduced received optical power conduce cannot decoding or error decoding. When the incident pulse's width is less than the chip duration, good encoding/decoding performance can be achieved. 相似文献
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We demonstrate a WDM compatible optical CDMA system incorporating 3D spectral phase–time encoding/decoding. We provide coding and decoding using binary [0, π] phase chips for six users at 6 Gb/s, with a single coded signal separated with an acceptable bit-error rate ≤10 ?9. The coding and decoding method is based on 3D coding of tightly spaced phase-locked laser lines that is compatible with conventional WDM networking. In optical CDMA systems, we propose to provide encoding and decoding done by converting Hadamard codes (used for conventional CDMA system) to the phase codes. We report that duo-binary modulation format is the best with adequate bandwidth compression. We confirm that better simulation results are reached in terms of the Q factor and bit error rate. 相似文献
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Fountain codes provide an efficient way to transfer information over erasure channels like the Internet. LT codes are the first codes fully realizing the digital fountain concept. They are asymptotically optimal rateless erasure codes with highly efficient encoding and decoding algorithms. In theory, for each encoding symbol of LT codes, its degree is randomly chosen according to a predetermined degree distribution, and its neighbours used to generate that encoding symbol are chosen uniformly at random. Practical implementation of LT codes usually realizes the randomness through pseudo-randomness number generator like linear congruential method. This paper applies the pseudo-randomness of chaotic sequence in the implementation of LT codes. Two Kent chaotic maps are used to determine the degree and neighbour(s) of each encoding symbol. It is shown that the implemented LT codes based on chaos perform better than the LT codes implemented by the traditional pseudo-randomness number generator. 相似文献
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为了解决常用数据采集产品体积较大的问题,选用一种体积小,转换速度快的多通道AD转换芯片ADS8638,设计了FPGA与芯片间的接口电路,并采用verilog语言编写了控制程序,以控制ADS8638芯片对各通道输入的模拟量进行AD转换。通过软件仿真验证、静态时序分析,仿真和分析结果表明,该软件功能、性能、时序正确。最后,将软件经过综合、布局布线后下载到ACTEL FPGA芯片中进行硬件系统测试,测试结果表明,本技术方案设计合理,功能可靠,降低了常用数据采集系统的体积和功耗,具有良好的实用价值。 相似文献
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