首页 | 本学科首页   官方微博 | 高级检索  
相似文献
 共查询到20条相似文献,搜索用时 234 毫秒
1.
一种实现MSD加法的光学方法   总被引:1,自引:0,他引:1  
三值光学计算机系统结合光强与光的偏振方向表示三值信息,其核心器件——三值逻辑光学处理器是按照降值设计理论完成的,该处理器能完成所有19683种二元三值逻辑运算.本文旨在提出一种实现加法运算的新方法——用三值逻辑光学处理器实现加法.为了解决加法的串行进位延时问题,使用改良符号数表示进行数据编码,从而实现全并行无进位加法.用三值光学计算机与改良符号数表示相结合的方法实现加法既能够充分发挥三值光学计算机位数巨大的优势以及三值逻辑光学处理器能完成所有二元三值逻辑运算的特性,同时又发挥了改良符号数加法的无进位特点.经实验证明该方法具有可行性和正确性,是实现光学加法器的一种新思路.  相似文献   

2.
阮昊  陈述春 《光子学报》1997,26(8):765-768
用单块电子俘获器件,以一种新方法一时域编码方法,实现了所有16种布尔逻辑运算.根据电子俘获材料的存贮和可擦除特性,按特定顺序进行一系列单元操作,可测到每种布尔逻辑函数,同一般光学逻辑处理器相比,这种处理器具有新的自由度一时域自由度,文末给出了实验结果.  相似文献   

3.
曹明翠  刘夏安 《光学学报》1989,9(12):129-1132
为了实现二进制加法符号替换规律,本文提出了一种简单的光逻辑系统,它仅包括一片二维列阵光学双稳器件.本实验采用同时具有NXOR和OR逻辑功能的透反射型ZnS光学双稳干涉滤光片作光逻辑器件.该光学逻辑系统完成了二进制加法四个符号替换规律的并行替换.光学系统采用固定的自由空间互连方法,具有光学硬件少,光功率损耗低,结构简单、实用的优点.  相似文献   

4.
王滨  余飞鸿 《光子学报》1998,27(9):813-818
冗余二进制法适合数字光学混合计算机.利用该法可以在常数时间内实现无进位的并行算数和,并建立内在的并行算数单元.本文在分析该方法的基础上,利用布尔偏振编码逻辑代数设计了高效光学冗余二进制加法操作系统.  相似文献   

5.
基于晶体双折射效应的光学逻辑处理器   总被引:1,自引:0,他引:1  
彭海峰  殷耀祖 《光学学报》1995,15(8):098-1101
利用晶体的双折射效应,发展起一种具有紧凑结构的光学逻辑处理器,实现对两个输入图像的所有16种逻辑操作。具有体积小,性能稳定及高包装密度等优点。也给出了实验结果。  相似文献   

6.
基于非线性定向耦合器的光二进制逻辑器件   总被引:2,自引:1,他引:1  
王又法  王子华 《光子学报》2000,29(3):223-226
本文提出了一种新的非双稳态光学逻辑器件,它由一个双端输入的非线性光波导耦合器产生相应的输入输出波形,再经过多级单端输入的非线性耦合器进行波形限幅和整形,以获得阶跃开关特性.通过理论计算说明适当选择输入条件,这种器件可以实现所有六种基本的二进制逻辑运算功能:与、或、与非、与或、异或和同或.  相似文献   

7.
本文提出了一种利用改进的符号数算法和多窗口解码光学符号代换法则实现多值矩阵计算的光学方法。并给出两个多比特改进的符号数矩阵外积计算的实验结果。这一方法具有精度高、速度快等特点。  相似文献   

8.
负二进制编码的光学阵列化复数运算   总被引:2,自引:1,他引:1  
李国强  刘立人  邵岚 《光学学报》1995,15(10):1409-1412
建立一套新颖的光学负二进制并行算法体系,包括加权-移位加法、列阵乘法等。一切运算无符号位、无进位、无再编码。利用两层阵列可实现高精度的复数运算,三层阵列可实现复数矩阵-矢量运算。该算法体系非常适合于光学执行。相应地,文中给出了两层列阵复数相乘光学系统及实验结果。原理上,该算法是可级联的。  相似文献   

9.
张家军  张莉 《光学学报》1993,13(3):44-247
提出一种基于光学逻辑运算的图像匹配新方法.若将输入图像与每一幅存贮的图像进行光学“异或”逻辑运算,并用光电方法探测逐点逻辑运算输出光强的总和,则与最小透射光强相对应的存贮图像就是输入图像的最佳匹配.我们采用了偏振编码和多成像技术来建立该方法的光电实现系统,并做出了实验结果.  相似文献   

10.
本文利用一种光学投影系统实现了具有三个二进制输入、双通道输出的光学并行逻辑运算。利用我们的方法可以实现三个二进制输入的所有256种布尔逻辑运算,由于是双通道输出,还可以方便地得到全加器输出结果。最后,本文还提出了一种实现输入图形实时编码的光学系统。  相似文献   

11.
The modified signed-digit (MSD) number system has been a topic of interest as it allows for parallel carry-free addition of two numbers for digital optical computing. In this paper, harmonic wavelet joint transform (HWJT)-based correlation technique is introduced for optical implementation of MSD trinary adder implementation. The realization of the carry-propagation-free addition of MSD trinary numerals is demonstrated using synthetic HWJT correlator model. It is also shown that the proposed synthetic wavelet filter-based correlator shows high performance in logic processing. Simulation results are presented to validate the performance of the proposed technique.  相似文献   

12.
A single-step optoelectronics symbolic substitution scheme to handle parallel modified signed-digit (MSD) arithmetic operations is proposed. Conversion algorithms from MSD numbers into a canonical MSD representation are provided. The canonical MSD numbers have the property that no two consecutive digits are non-zero. The addition operation of two CMSD numbers is performed in one step. It will be shown that through the use of CMSD representation, the number of symbolic substitution rules in an optical content-addressable memory (CAM) based system is significantly reduced. The number of symbolic substitution rules can be further reduced to an optimum value through a proposed shared content-addressable memory optical set-up. Further, the proposed optical scheme doubles the storage efficiency of the shared content-addressable memory.  相似文献   

13.
The need for increasingly high-speed digital optical systems and optical processors demands ultra-fast all-optical logic and arithmetic units. In this paper, we combine the attractive and powerful parallelism property of the modified signed-digit (MSD) number representation with the ultra-fast all-optical switching property of the semiconductor optical amplifier and Mach-Zehnder interferometer (SOA-MZI) to design and implement all-optical MSD adder/subtracter circuits. Non-minimized and minimized techniques are presented to design and realize efficient circuits to perform arithmetic operations. Several all-optical circuits’ designs are proposed with the objective to minimize the number of the SOA-MZI switches, the time delay units in the adders, and other optical elements. To use the switching property of the SOA-MZI structure, two bits per digit binary encoding for each of the trinary MSD digits are used. The proposed optical circuits will be very helpful in developing hardware modules for optical digital computing processors.  相似文献   

14.
In this work, a three-step modified signed-digit (MSD) addition by using binary logic operations is proposed. Each input digit is encoded with two binary bits. Through binary logic operations, all of the weight and transfer digits and the final sum digits represented with the same encoding scheme will be generated. The operations can be performed at each digit position in parallel. In our suggested optical arithmetic and logic unit (ALU), a single electron trapping (ET) device is employed to serve as the binary logic device. This technique based on ET logic possesses the advantage of high signal-to-noise ratio (SNR). The optoelectronic system can be constructed in a simple, compact and general-purpose form.  相似文献   

15.
A simple one-step fully parallel trinary signed-digit arithmetic is proposed for parallel optical computing. This technique performs multidigit carry-free addition and borrow-free subtraction in constant time. The trinary signed-digit arithmetic operations are based on redundant bit representation of the digits. Optical implementation of the proposed arithmetic can be carried out using correlation or matrix multiplication based schemes. An efficient matrix multiplication based optical implementation that employs a fixed number of minterms for any operand length is developed. It is shown that only 30 minterms (less than recently reported techniques) are enough for implementing the one-step trinary addition and subtraction.  相似文献   

16.
A new design approach for a three-step modified signed-digit (MSD) adder is presented that can be optically implemented using binary logic gates. The proposed scheme depends on encoding each MSD digits into a pair of binary digits using a two-state and multi-position encoding scheme. The proposed design algorithm depends on constructing the addition truth table of binary-coded MSD numbers and then using Karnaugh map to achieve output minimization. The optical binary logic gates are obtained by simply programming the decoding masks of a shadow-casting-based optical logic gate system. The proposed scheme results in a simple, compact, and efficient optical binary gate-based parallel addition system.  相似文献   

17.
We propose here a new optical modified signed-digit (MSD) adder module based on bit plane pattern encoding of MSD digits and pattern operations. The pattern operations required in the algorithm are duplication, combination and shifting. They are simply performed by using optical components such as beam splitters, mirrors and parallel plates, instead of optical logic arrays. An optical MSD adder module comprised of six properly interacting blocks with all optical components packaged on a common substrate is presented in detail. We analyze the system errors caused by manufacture and alignment of optical components, the information throughput, the intensity nonuniformity and the system volume of the adder module.  相似文献   

18.
In this paper, we present improved all-optical circuits that implement ultra-fast adders based on the carry-free property of the modified signed-digit (MSD) number representation. The all-optical realizations are based on semiconductor optical amplifier (SOA) and Mach-Zehnder interferometer (MZI) switches, which represent one of the most promising solutions due to their compact size, thermal stability and low power operation. Several all-optical circuit designs are proposed with the objective to minimize the number of the SOA-MZI switches, the time delay in the adders and some other optical elements. The proposed circuits are more efficient comparing to previously published ones in terms of the number of optical components (less by 50%) as well as the operational speed (faster by 50%).  相似文献   

19.
This study proposes and construct a primitive quantum arithmetic logic unit (qALU) based on the quantum Fourier transform (QFT). The qALU is capable of performing arithmetic ADD (addition) and logic NAND gate operations. It designs a scalable quantum circuit and presents the circuits for driving ADD and NAND operations on two-input and four-input quantum channels, respectively. By comparing the required number of quantum gates for serial and parallel architectures in executing arithmetic addition, it evaluates the performance. It also execute the proposed quantum Fourier transform-based qALU design on real quantum processor hardware provided by IBM. The results demonstrate that the proposed circuit can perform arithmetic and logic operations with a high success rate. Furthermore, it discusses in detail the potential implementations of the qALU circuit in the field of computer science, highlighting the possibility of constructing a soft-core processor on a quantum processing unit.  相似文献   

20.
The inherent parallelism of optical signal is an advantageous feature for high-speed computations and other digital logic operations. Different techniques have been proposed for performing arithmetic, algebraic and logic operations using light as the information-carrier. Here we propose a new method for Serial Data Transfer between Registers using optical non-linear material. This system is all-optical in nature. Optical NAND gate and NOT gate are the basic building blocks of this system.  相似文献   

设为首页 | 免责声明 | 关于勤云 | 加入收藏

Copyright©北京勤云科技发展有限公司  京ICP备09084417号