Oxygen Pressure Dependence of Properties of Epitaxial LaAlO3 Films Grown on Si （100）

Heteroepitaxial LaAlO3 films were grown on a SrTiO3/Si (100) substrate by laser molecular beam epitaxy under different oxygen pressures, and their properties such as crystallinity and electrical characteristics were experimentally investigated using the various measurement methods. The results show that most properties depend mainly on the deposition oxygen pressure. The crystallinity and the C-V and I-V characteristics can be greatly improved with the increasing oxygen deposition pressure. Moreover, after annealed at 1050~C in N2 ambient, the C-V and I-V characteristics of LAO films deposited at the lower oxygen pressure are also improved due to the decrease of oxygen vacancies in LAO films.     

Transient Hole Trapping in Individual GeSi Quantum Dot Grown on Si（001） Studied by Conductive Atomic Force Microscopy

Electrical properties of individual self-assembled GeSi quantum dots grown on Si substrates are investigated by using conductive atomic force microscopy at room temperature. By controlling the bias voltage sweep in a certain fast sweep rate range, a novel current peak is observed in the current-voltage characteristics of the quantum dots. The current peaks are detectable only during the backward voltage sweep immediately after a forward sweep. The current peak position and intensity are found to depend strongly on the voltage sweep conditions. This kind of current-voltage characteristic under fast sweep is very different from the ordinary steady state current behaviour of quantum dots measured previously. trapping in the potential well formed bottom Si substrate. The origin of this phenomenon by the quantum dot sandwiched can be attributed to the transient hole between the native oxide layer and the     

CdS/Si nanofilm heterojunctions based on amorphous silicon films:Fabrication,structures,and electrical properties

Shortening the distance between the depletion region and the electrodes to reduce the trapped probability of carriers is a useful approach for improving the performance of heterojunction.The CdS/Si nanofilm heterojunctions are fabricated by using the radio frequency magnetron sputtering method to deposit the amorphous silicon nanofilms and Cd S nanofilms on the ITO glass in turn.The relation of current density to applied voltage(I-V)shows the obvious rectification effect.From the analysis of the double logarithm I-V curve it follows that below~2.73 V the electron behaviors obey the Ohmic mechanism and above~2.73 V the electron behaviors conform to the space charge limited current(SCLC)mechanism.In the SCLC region part of the traps between the Fermi level and conduction band are occupied,and with the increase of voltage most of the traps are occupied.It is believed that Cd S/Si nanofilm heterojunction is a potential candidate in the field of nano electronic and optoelectronic devices by optimizing its fabricating procedure.     

Ferroelectric effect and equivalent polarization charge model of PbZr_(0.2)Ti_(0.8)O_3 on AlGaN/GaN MIS-HEMT

PbZr_(0.2)Ti_(0.8)O_3(PZT) gate insulator with the thickness of 30 nm is grown by pulsed laser deposition(PLD) in AlGa N/Ga N metal–insulator–semiconductor high electron mobility transistors(MIS-HEMTs). The ferroelectric effect of PZT Al Ga N/Ga N MIS-HEMT is demonstrated. The polarization charge in PZT varies with different gate voltages. The equivalent polarization charge model(EPCM) is proposed for calculating the polarization charge and the concentration of two-dimensional electron gas(2 DEG). The threshold voltage(Vth) and output current density(IDS) can also be obtained by the EPCM. The theoretical values are in good agreement with the experimental results and the model can provide a guide for the design of the PZT MIS-HEMT. The polarization charges of PZT can be modulated by different gate-voltage stresses and the Vthhas a regulation range of 4.0 V. The polarization charge changes after the stress of gate voltage for several seconds. When the gate voltage is stable or changes at high frequency, the output characteristics and the current collapse of the device remain stable.     

Quantum transport characteristics in single and multiple N-channel junctionless nanowire transistors at low temperatures

Single and multiple n-channel junctionless nanowire transistors(JNTs) are fabricated and experimentally investigated at variable temperatures. Clear current oscillations caused by the quantum-confinement effect are observed in the curve of drain current versus gate voltage acquired at low temperatures(10 K–100 K) and variable drain bias voltages(10 mV–90 mV). Transfer characteristics exhibit current oscillation peaks below flat-band voltage(VFB) at temperatures up to 75 K,which is possibly due to Coulomb-blocking from quantum dots, which are randomly formed by ionized dopants in the just opened n-type one-dimensional(1D) channel of silicon nanowires. However, at higher voltages than VFB, regular current steps are observed in single-channel JNTs, which corresponds to the fully populated subbands in the 1D channel. The subband energy spacing extracted from transconductance peaks accords well with theoretical predication. However, in multiple-channel JNT, only tiny oscillation peaks of the drain current are observed due to the combination of the drain current from multiple channels with quantum-confinement effects.     

Characterization of ion-implanted 4H-SiC Schottky barrier diodes

Ion-implantation layers are fabricated by multiple nitrogen ion-implantations (3 times for sample A and 4 times for sample B) into a p-type 4H-SiC epitaxial layer. The implantation depth profiles are calculated by using the Monte Carlo simulator TRIM. The fabrication process and the I-V and C-V characteristics of the lateral Ti/4H-SiC Schottky barrier diodes (SBDs) fabricated on these multiple box-like ion-implantation layers are presented in detail. Measurements of the reverse I-V characteristics demonstrate a low reverse current, which is good enough for many SiC-based devices such as SiC metal-semiconductor field-effect transistors (MESFETs), and SiC static induction transistors (SITs). The parameters of the diodes are extracted from the forward I-V and C-V characteristics. The values of ideality factor n of SBDs for samples A and B are 3.0 and 3.5 respectively, and the values of series resistance R s are 11.9 and 1.0 k respectively. The values of barrier height B of Ti/4H-SiC are 0.95 and 0.72 eV obtained by the I-V method and 1.14 and 0.93 eV obtained by the C-V method for samples A and B respectively. The activation rates for the implanted nitrogen ions of samples A and B are 2% and 4% respectively extracted from C-V testing results.     

Ab initio investigation of boron nanodevices: conductances of the different geometric conformations

Conductances of different geometric conformations of boron ribbon devices are calculated by the ab initio method. The I-V characteristics of three devices are rather different due to the difference in structure. The current of the hexagonal boron device is the largest and increases nonlinearly. The current of the hybrid hexagon-triangle boron device displays a large low-bias current and saturates at a value of about 5.2 μA. The current of the flat triangular boron flake exhibits a voltage gap at low bias and rises sharply with increasing voltage. The flat triangular boron device can be either conducting or insulating, depending on the field.     

Structural and electrical characterization of annealed Si1-xCx/SiC thin film prepared by magnetron sputtering

Si-rich Sil-xCx/SiC multilayer thin films are prepared using magnetron sputtering, subsequently followed by thermal annealing in the range of 800-1200 ℃. The influences of annealing temperature （Ta） on the formation of Si and/or SiC nanocrystals （NCs） and on the electrical characteristics of the multilayer film are investigated by using a variety of analytical techniques, including X-ray diffraction （XRD）, Raman spectroscopy and Fourier transform infrared spectrometry （FT-IR）, current-voltage （I-V） technique, and capacitance-voltage （C-V） technique. XRD and Raman analyses indicate that Si NCs begin to form in samples for Ta _ 800 ~C. At annealing temperatures of 1000 ℃ or higher, the formation of Si NCs is accompanied by the formation of SiC NCs. With the increase in the annealing temperature, the shift of FT-IR Si-C bond absorption spectra toward a higher wave number along with the change of band shape can be explained by a Si-C transitional phase between the loss of substitutional carbon and the formation of SiC precipitates and a precursor for the growth of SiC crystalline. The C-V and I-V results indicate that the interface quality of Si1-xCx/SiC multilayer film is improved significantly and the leakage current is reduced rapidly for Ta ≥ 1000 ℃, which can be ascribed to the formation of Si and SiC NCs.     

Effects of notch structures on DC and RF performances of AlGaN/GaN high electron mobility transistors

The effects of various notch structures on direct current(DC) and radio frequency(RF) performances of AlGaN/GaN high electron mobility transistors(HEMTs) are analyzed.The AlGaN/GaN HEMTs,each with a 0.8-μm gate length,50-μm gate width,and 3-μm source-drain distance in various notch structures at the AlGaN/GaN barrier layer,are manufactured to achieve the desired DC and RF characteristics.The maximum drain current(I_(ds,max)),pinch-off voltage(V_(th)),maximum transconductance(g_m),gate voltage swing(GVS),subthreshold current,gate leakage current,pulsed I-V characteristics,breakdown voltage,cut-off frequency(f_T),and maximum oscillation frequency(f_(max)) are investigated.The results show that the double-notch structure HEMT has a 30% improvement of gate voltage swing,a 42.2% improvement of breakdown voltage,and a 9% improvement of cut-off frequency compared with the conventional HEMT.The notch structure also has a good suppression of the current collapse.     

Analysis on degradation mechanisms of normally-off p-GaN gate AlGaN/GaN high-electron mobility transistor

The degradation mechanisms of enhancement-mode p-GaN gate AlGaN/GaN high-electron mobility transistor was analyzed extensively,by means of drain voltage stress and gate bias stress.The results indicate that:(ⅰ) High constant drain voltage stress has only a negligible impact on the device electrical parameters,with a slightly first increase and then decrease in output current;(ⅱ) A negative shift of threshold voltage and increased output current were observed in the device subjected to forward gate bias stress,which is mainly ascribed to the hole-trapping induced by high electric field across the p-GaN/AlGaN interface;(ⅲ) The analyzed device showed an excellent behavior at reverse gate bias stress,with almost unaltered threshold voltage,output current,and gate leakage current,exhibiting a large gate swing in the negative direction.The results are meaningful and valuable in directing the process optimization towards a high voltage and high reliable enhanced AlGaN/GaN high-electron mobility transistor.