Study on two-dimensional analytical models for symmetrical gate stack dual gate strained silicon MOSFETs

Based on the exact resultant solution of two-dimensional Poisson’s equation, the novel two-dimensional models, which include surface potential, threshold voltage, subthreshold current and subthreshold swing, have been developed for gate stack symmetrical double-gate strained-Si MOSFETs. The models are verified by numerical simulation. Besides offering the physical insight into device physics, the model provides the basic designing guidance of further immunity of short channel effect of complementary metal-oxide-semiconductor (CMOS)-based device in a nanoscale regime.     

A two-dimensional analytical subthreshold behavior model for junctionless dual-material cylindrical surrounding-gate MOSFETs

A two-dimensional analytical subthreshold behavior model for junctionless dual-material cylindrical surrounding- gate （JLDMCSG） metal-oxide-semiconductor field-effect transistors （MOSFETs） is proposed. It is derived by solving the two-dimensional Poisson＇s equation in two continuous cylindrical regions with any simplifying assumption. Using this analytical model, the subthreshold characteristics of JLDMCSG MOSFETs are investigated in terms of channel electro- static potential, horizontal electric field, and subthreshold current. Compared to junctionless single-material cylindrical surrounding-gate MOSFETs, JLDMCSG MOSFETs can effectively suppress short-channel effects and simultaneously im- prove carrier transport efficiency. It is found that the subthreshold current of JLDMCSG MOSFETs can be significantly reduced by adopting both a thin oxide and thin silicon channel. The accuracy of the analytical model is verified by its good agreement with the three-dimensional numerical simulator ISE TCAD.     

Two-dimensional models of threshold voltage and subthreshold current for symmetrical double-material double-gate strained Si MOSFETs

The two-dimensional models for symmetrical double-material double-gate(DM-DG) strained Si(s-Si) metal–oxide semiconductor field effect transistors(MOSFETs) are presented. The surface potential and the surface electric field expressions have been obtained by solving Poisson's equation. The models of threshold voltage and subthreshold current are obtained based on the surface potential expression. The surface potential and the surface electric field are compared with those of single-material double-gate(SM-DG) MOSFETs. The effects of different device parameters on the threshold voltage and the subthreshold current are demonstrated. The analytical models give deep insight into the device parameters design. The analytical results obtained from the proposed models show good matching with the simulation results using DESSIS.     

A threshold voltage analytical model for high-k gate dielectric MOSFETs with fully overlapped lightly doped drain structures

We investigate the influence of voltage drop across the lightly doped drain(LDD) region and the built-in potential on MOSFETs,and develop a threshold voltage model for high-k gate dielectric MOSFETs with fully overlapped LDD structures by solving the two-dimensional Poisson’s equation in the silicon and gate dielectric layers.The model can predict the fringing-induced barrier lowering effect and the short channel effect.It is also valid for non-LDD MOSFETs.Based on this model,the relationship between threshold voltage roll-off and three parameters,channel length,drain voltage and gate dielectric permittivity,is investigated.Compared with the non-LDD MOSFET,the LDD MOSFET depends slightly on channel length,drain voltage,and gate dielectric permittivity.The model is verified at the end of the paper.     

The influence and explanation of fringing-induced barrier lowering on sub-100 nm MOSFETs with high-k gate dielectrics

The fringing-induced barrier lowering(FIBL) effect of sub-100 nm MOSFETs with high-k gate dielectrics is investigated using a two-dimensional device simulator.An equivalent capacitance theory is proposed to explain the physics mechanism of the FIBL effect.The FIBL effect is enhanced and the short channel performance is degraded with increasing capacitance.Based on equivalent capacitance theory,the influences of channel length,junction depth,gate/lightly doped drain(LDD) overlap length,spacer material and spacer width on FIBL is thoroughly investigated.A stack gate dielectric is presented to suppress the FIBL effect.     

An analytical threshold voltage model for dual-strained channel PMOSFET

Based on the analysis of vertical electric potential distribution across the dual-channel strained p-type Si/strained Si 1-x Ge x /relaxd Si 1-y Ge y (s-Si/s-SiGe/Si 1-y Ge y) metal-oxide-semiconductor field-effect transistor (PMOSFET),an-alytical expressions of the threshold voltages for buried channel and surface channel are presented.And the maximum allowed thickness of s-Si is given,which can ensure that the strong inversion appears earlier in the buried channel (compressive strained SiGe) than in the surface channel (tensile strained Si),because the hole mobility in the buried channel is higher than that in the surface channel.Thus they offer a good accuracy as compared with the results of device simulator ISE.With this model,the variations of threshold voltage and maximum allowed thickness of s-Si with design parameters can be predicted,such as Ge fraction,layer thickness,and doping concentration.This model can serve as a useful tool for p-channel s-Si/s-SiGe/Si 1-y Ge y metal-oxide-semiconductor field-effect transistor (MOSFET) designs.     

Novel vertical stack HCMOSFET with strained SiGe/Si quantum channel

A novel vertical stack heterostructure CMOSFET is investigated, which is structured by strained SiGe/Si with a hole quantum well channel in the compressively strained Si量子信道 异质结构 CMOSFET 量子论 量子阱strained SiGe/Si, quantum well channel, heterostructure CMOSFET, poly-SiGe gateProject supported by the Preresearch from National Ministries and Commissions (Grant Nos 51408061104DZ01, 51439010904DZ0101).2/2/2006 12:00:00 AM2006-01-022006-03-16A novel vertical stack heterostructure CMOSFET is investigated, which is structured by strained SiGe/Si with a hole quantum well channel in the compressively strained Sil-xGex layer for p-MOSFET and an electron quantum well channel in the tensile strained Si layer for n-MOSFET. The device possesses several advantages including： 1） the integration of electron quantum well channel with hole quantum well channel into the same vertical layer structure; 2） the gate work function modifiability due to the introduction of poly-SiGe as a gate material; 3） better transistor matching; and 4） flexibility of layout design of CMOSFET by adopting exactly the same material lays for both n-channel and p-channel. The MEDICI simulation result shows that p-MOSFET and n-MOSFET have approximately the same matching threshold voltages. Nice performances are displayed in transfer characteristic, transconductance and cut-off frequency. In addition, its operation as an inverter confirms the CMOSFET structured device to be normal and effective in function.     

Analytical analysis of surface potential for grooved-gate MOSFET

The improvement of the characteristics of grooved-gate MOSFETs compared to the planar devices is attributed to the corner effect of the surface potential along the channel. In this paper we propose an analytical model of the surface potential distribution based on the solution of two-dimensional Poisson equation in cylindrical coordinates utilizing the cylinder approximation and the structure parameters such as the concave corner $\theta _0 $. The relationship between the minimum surface potential and the structure parameters is theoretically analysed. Results confirm that the bigger the concave corner, the more obvious the corner effect. The corner effect increases the threshold voltage of the grooved-gate MOSFETs, so the better is the short channel effect (SCE) immunity.     

Effect of interface roughness on the carrier transport in germanium MOSFETs investigated by Monte Carlo method

Interface roughness strongly influences the performance of germanium metal--organic--semiconductor field effect transistors (MOSFETs). In this paper, a 2D full-band Monte Carlo simulator is used to study the impact of interface roughness scattering on electron and hole transport properties in long- and short- channel Ge MOSFETs inversion layers. The carrier effective mobility in the channel of Ge MOSFETs and the in non-equilibrium transport properties are investigated. Results show that both electron and hole mobility are strongly influenced by interface roughness scattering. The output curves for 50~nm channel-length double gate n and p Ge MOSFET show that the drive currents of n- and p-Ge MOSFETs have significant improvement compared with that of Si n- and p-MOSFETs with smooth interface between channel and gate dielectric. The $82\%$ and $96\%$ drive current enhancement are obtained for the n- and p-MOSFETs with the completely smooth interface. However, the enhancement decreases sharply with the increase of interface roughness. With the very rough interface, the drive currents of Ge MOSFETs are even less than that of Si MOSFETs. Moreover, the significant velocity overshoot also has been found in Ge MOSFETs.     

Analysis of flatband voltage shift of metal/high-k/SiO2/Si stack based on energy band alignment of entire gate stack

A theoretical model of flatband voltage(VFB) of metal/high-k/SiO2/Si stack is proposed based on band alignment of entire gate stack, i.e., the VFBis obtained by simultaneously considering band alignments of metal/high-k, high-k/SiO2 and SiO2/Si interfaces, and their interactions. Then the VFBof TiN/HfO2/SiO2/Si stack is experimentally obtained and theoretically investigated by this model. The theoretical calculations are in good agreement with the experimental results.Furthermore, both positive VFBshift of TiN/HfO2/SiO2/Si stack and Fermi level pinning are successfully interpreted and attributed to the dielectric contact induced gap states at TiN/HfO2 and HfO2/SiO2 interfaces.     

堆叠栅介质对称双栅单Halo应变Si金属氧化物半导体场效应管二维模型

提出了一种堆叠栅介质对称双栅单Halo应变Si金属氧化物半导体场效应管(metal-oxide semiconductor field effect transistor,MOSFET)新器件结构.采用分区的抛物线电势近似法和通用边界条件求解二维泊松方程,建立了全耗尽条件下的表面势和阈值电压的解析模型.该结构的应变硅沟道有两个掺杂区域,和常规双栅器件(均匀掺杂沟道)比较,沟道表面势呈阶梯电势分布,能进一步提高载流子迁移率;探讨了漏源电压对短沟道效应的影响;分析得到阈值电压随缓冲层Ge组分的提高而降低,随堆叠栅介质高k层介电常数的增大而增大,随源端应变硅沟道掺杂浓度的升高而增大,并解释了其物理机理.分析结果表明:该新结构器件能够更好地减小阈值电压漂移,抑制短沟道效应,为纳米领域MOSFET器件设计提供了指导.     

Two-dimensional analytical subthreshold model of graded channel DG FD SOI n-MOSFET with gate misalignment effect

A two-dimensional (2-D) analytical subthreshold model is developed for a graded channel double gate (DG) fully depleted SOI n-MOSFET incorporating a gate misalignment effect. The conformal mapping transformation (CMT) approach has been used to provide an accurate prediction of the surface potential, electric field, threshold voltage and subthreshold behavior of the device, considering the gate misalignment effect to be on both source and drain side. The model is applied to both uniformly doped (UD) and graded channel (GC) DG MOSFETs. The results of an analytical model agree well with 3-D simulated data obtained by ATLAS-3D device simulation software.     

Fabrication of Ge-channel MOSFETs by using replacement gate process and selective epitaxial growth

We fabricated Ge-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) by using replacement gate process and selective epitaxial growth. In our method, thin Ge layers were selectively grown on the channel region of MOSFETs after the removal of a sacrificial gate stack structure and the etching of the channel region. Ge layers with a smooth surface and a good morphology could be obtained by using the thin Si_0.5Ge_0.5 buffer layer. Dislocations were observed in the epitaxial layers and near the interface between the epitaxial layer and the substrates. We consider that these dislocations degrade the device performance. Although the electrical characteristics of the obtained MOSFETs need further improvement, our method is one of the promising candidates for the practical fabrication process of Ge-channel MOSFETs.     

Physics of fluctuation processes in downscaled silicon MOSFETs

Physical mechanics of fluctuation processes in advanced submicron and decananometer MOSFETs (metal-oxide-semiconductor field-effect transistors) including the ultra-thin film SOI (siliconon-insulator) devices using strained silicon films are reviewed. The review is substantially based on the results obtained by the authors. It is shown that the following drastic changes occur in the nature and parameters of noise in such devices as a result of their downscaling when the gate oxide thickness and the channel length and width are decreased, the SOI substrates are used, the silicon film thickness is reduced, the film doping level is varied, the strained silicon films are employed, etc. Firstly, the Lorentzian components can appear in the current noise spectra. Those components are due to (i) electron tunneling from the valence band through the gate oxide in the SOI MOSFETs of a sufficiently thin gate oxide (LKE-Lorentzians); (ii) Nyquist fluctuations generated in the source and drain regions near the back Si/SiO₂ interface in the SOI MOSFETs (BGI Lorentzians); (iii) electron exchange between the channel and some single trap in the gate oxide of the transistors with sufficiently small length and width of the channel (RTS Lorentzians). Secondly, the 1/f-noise level can increase due to (i) the appearance of recombination processes near the Si/SiO₂ interface activated by the currents of electron tunneling from the valence band; (ii) an increase in the trap density in the gate oxide of the devices fabricated on the biaxially tensile-strained silicon films; (iii) the contribution of the 1/f fluctuations of the current flowing through the gate oxide as a result of electron tunneling from the conduction band. At the same time, the 1/f-noise level may decrease due to a decrease in the trap density in the gate oxide of the transistors fabricated on the uniaxially tensile-strained silicon films. Moreover, a 1/f ^1.7 component may appear in the noise spectra for the transistors of a sufficiently thin gate oxide, whose component is due to charge fluctuations on the defects located near the interface between the gate polysilicon and the gate oxide.     

A two-dimensional analytical analysis of subthreshold behavior to study the scaling capability of nanoscale graded channel gate stack DG MOSFETs

In this paper, a new nanoscale graded channel gate stack (GCGS) double-gate (DG) MOSFET structure and its 2-D analytical model have been proposed, investigated and expected to suppress the short-channel-effects (SCEs) and improve the subthreshold performances for nanoelectronics applications. The model predicts a shift, increasing potential barrier, in the surface potential profile along the channel, which ensures a reduced threshold voltage roll-off and DIBL effects. In the proposed structure, the subthreshold current and subthreshold swing characteristics are greatly improved in comparison with the conventional DG MOSFETs. The developed approaches are verified and validated by the good agreement found with the numerical simulation. (GCGS) DG MOSFET can alleviate the critical problem and further improve the immunity of SCEs of CMOS-based devices in the nanoscale regime.     

Analytical modeling of subthreshold current and subthreshold swing of short-channel triple-material double-gate (TM-DG) MOSFETs

An analytical model for subthreshold current and subthreshold swing of short-channel triple-material double-gate (TM-DG) MOSFETs is presented in this paper. Both the drift and diffusion components of current densities are considered for the modeling of subthreshold current. Virtual cathode concept of DG MOSFETs is utilized to model the subthreshold swing of TM-DG MOSFETs. The effect of different length ratios of the three channel regions under three different gate materials of device on the subthreshold current and subthreshold swing of the short-channel TM-DG MOSFETs have been discussed. The dependencies of subthreshold current and subthreshold swing on various device parameters have been studied. The simulation data obtained by using the commercially available 2D device simulation software ATLAS™ has been used to validate the present model.     

Ge metal oxide semiconductor field effect transistors with optimized Si cap and HfSiO2 high-k metal gate stacks

High mobility metal-oxide-semiconductor-field-effect-transistors (MOSFETs) are demonstrated on high quality epitaxial Si_0.75Ge_0.25 films selectively grown on Si (100) substrates. With a Si cap processed on Si_0.75Ge_0.25 channels, HfSiO₂ high-k gate dielectrics exhibited low C–V hysteresis (<10 mV), interface trap density (7.5 × 10¹⁰), and gate leakage current (∼10⁻²A/cm² at an EOT of 13.4 Å), which are comparable to gate stack on Si channels. The mobility enhancement afforded intrinsically by the Si_0.75Ge_0.25 channel (60%) is further increased by a Si cap (40%) process, resulting in a combined ∼100% enhancement over Si channels. The Si cap process also mitigates the low potential barrier issues of Si_0.75Ge_0.25 channels, which are major causes of the high off-state current of small band gap energy Si_0.75Ge_0.25 pMOSFETs, by improving gate control over the channel.     

Analytical modeling and simulation of subthreshold characteristics of back-gated SSGOI and SSOI MOSFETs: A comparative study

The Silicon–Germanium-on-Insulator (SGOI) and Silicon-on-Insulator (SOI) based MOS structures are spearheading the strained-Si technology. The present work compares the subthreshold characteristics of two short-channel back-gated (BG) strained-Si-on-SGOI (SSGOI) and BG strained-Si-on-Insulator (SSOI) MOSFETs, and provides some solutions to overcome the degradation in subthreshold characteristics with the unrelenting downscaling of the devices. Subthreshold behaviors of the MOS structures are based on surface potential model which is determined by solving the 2D Poisson's equation with suitable boundary conditions by evanescent mode analysis for both of the MOS structures. The closed form expressions for threshold voltage, subthreshold current and subthreshold swing have been derived for symmetrical as well as independent gate operation (IGO). In addition, the Electrostatic integrity (EI) factors for SSOI and SSGOI MOS structures have been estimated and compared with Double-Gate (DG) MOSFET. The numerical simulation results, obtained by ATLAS?, a 2D device simulator from Silvaco, have been used to assess the validity of the models.