高k栅介质对肖特基源漏超薄体SOI MOSFET性能的影响

研究了高k栅介质对肖特基源漏超薄体SOI MOSFET性能的影响.随着栅介质介电常数增大,肖特基源漏(SBSD) SOI MOSFET的开态电流减小,这表明边缘感应势垒降低效应(FIBL)并不是对势垒产生影响的主要机理.源端附近边缘感应势垒屏蔽效应(FIBS)是SBSD SOI MOSFET开态电流减小的主要原因.同时还发现,源漏与栅是否对准,高k栅介质对器件性能的影响也不相同.如果源漏与栅交叠,高k栅介质与硅衬底之间加入过渡层可以有效地抑制FIBS效应.如果源漏偏离栅,采用高k侧墙并结合堆叠栅结构,可以提高驱动电流.分析结果表明,来自栅极的电力线在介电常数不同的材料界面发生两次折射.根据结构参数的不同可以调节电力线的疏密,从而达到改变势垒高度,调节驱动电流的目的. 关键词： k栅介质')" href="#">高k栅介质 肖特基源漏(SBSD) 边缘感应势垒屏蔽(FIBS) 绝缘衬底上的硅(SOI)     

高k栅介质应变Si SOI MOSFET的阈值电压解析模型

在结合应变Si,高k栅和SOI结构三者的优点的基础上,提出了一种新型的高k栅介质应变Si全耗尽SOI MOSFET结构.通过求解二维泊松方程建立了该新结构的二维阈值电压模型,在该模型中考虑了影响阈值电压的主要参数.分析了阈值电压与弛豫层中的Ge组分、应变Si层厚度的关系.研究结果表明阈值电压随弛豫层中Ge组分的提高和应变Si层的厚度增加而降低.此外,还分析了阈值电压与高k栅介质的介电常数和应变Si层的掺杂浓度的关系.研究结果表明阈值电压随高k介质的介 关键词： 应变Si k栅')" href="#">高k栅 短沟道效应 漏致势垒降低     

低工作电压聚噻吩薄膜晶体管

以高掺杂Si单晶片作为衬底且充当栅电极,采用磁控溅射法在硅片上沉积HfTiO薄膜作为栅介质层,聚三己基噻吩(P3HT)薄膜作为半导体活性层,金属Au作为源、漏电极,并采用十八烷基三氯硅烷(OTS)对栅介质层表面修饰,在空气环境下成功地制备出聚合物薄膜晶体管(PTFT).PTFT器件测试结果表明,该晶体管在低的驱动电压(<-1 V)下仍呈现出良好的饱和行为,其阈值电压和有效场效应迁移率分别为0.4 V和2.2×10^-2 cm²/V ·s.通过对金属-聚合物-氧化物 关键词： 聚合物薄膜晶体管 聚三己基噻吩 场效应迁移率 k栅介质')" href="#">高k栅介质     

高k介质异质栅全耗尽SOI MOSFET二维解析模型

为了研究高介电常数(高k)栅介质材料异质栅中绝缘衬底上的硅和金属-氧化物-硅场效应晶体管的短沟道效应,为新结构器件建立了全耗尽条件下表面势和阈值电压的二维解析模型.模型中考虑了各种主要因素的影响,包括不同介电常数材料的影响,栅金属长度及其功函数变化的影响,不同漏电压对短沟道效应的影响.结果表明,沟道表面势中引入了阶梯分布,因此源端电场较强;同时漏电压引起的电势变化可以被屏蔽,抑制短沟道效应.栅介电常数增大,也可以较好的抑制短沟道效应.解析模型与数值模拟软件ISE所得结果高度吻合. 关键词： 异质栅 绝缘衬底上的硅 阈值电压 解析模型     

高迁移率聚合物薄膜晶体管

以高掺杂Si单晶片作为栅电极, 热生长SiO₂作为栅介质层, 聚三己基噻吩薄膜作为半导体活性层, Au作为源、漏电极, 并采用十八烷基三氯硅烷（OTS）对栅介质表面改性, 在空气环境下成功地制备出高性能聚合物薄膜晶体管. 结果表明, 通过采用OTS对栅介质层表面修饰大幅度地改善了聚合物薄膜晶体管的电性能, 器件的场效应迁移率高达0.02 cm²/（Vs）, 开关电流比大于10⁵. 关键词： 聚合物薄膜晶体管 聚三己基噻吩 场效应迁移率 表面修饰     

具有HfN/HfO2栅结构的p型MOSFET中的负偏置-温度不稳定性研究

研究了HfN/HfO₂高K栅结构p型金属-氧化物-半导体(MOS)晶体管(MOSFET)中，负 偏置-温度应力引起的阈值电压不稳定性(NBTI)特征.HfN/HfO₂高K栅结构的等效 氧化层厚度(EOT)为1.3nm，内含原生缺陷密度较低.研究表明，由于所制备的HfN/HfO₂ 高K栅结构具有低的原生缺陷密度，因此在p-MOSFET器件中观察到的NBTI属HfN/HfO2高K栅结构的本征特征，而非工艺缺陷引起的；进一步研究表明，该HfN/HfO₂高K栅结构中观察到的NBTI与传统的SiO₂基栅介质p-MOSFET器件中观察 到的NBTI具有类似的特征，可以被所谓的反应-扩散(R-D)模型表征： HfN/HfO₂ 栅结构p-MOSFET器件的NBTI效应的起源可以归为衬底注入空穴诱导的界面反应机理，即在负 偏置和温度应力作用下，从Si衬底注入的空穴诱导了Si衬底界面Si-H键断裂这一化学反应的 发生，并由此产生了Si^＋陷阱在Si衬底界面的积累和H原子在介质层内部的扩散 ，这种Si^＋陷阱的界面积累和H原子的扩散导致了器件NBTI效应的发生. 关键词： 高K栅介质 负偏置-温度不稳定性(NBTI) 反应-扩散(R-D)模型     

基于P掺杂SiO2为栅介质的超低压侧栅薄膜晶体管

在室温下利用等离子体增强化学气相沉积法(PECVD)制备的颗粒膜P掺杂SiO₂为栅介质, 使用磁控溅射方法利用一步掩模法制备出一种新型结构的侧栅薄膜晶体管. 由于侧栅薄膜晶体管具有独特的结构, 在射频磁控溅射过程中, 仅仅利用一块镍掩模板, 无需复杂的光刻步骤, 就可同时沉积出氧化铟锡(ITO)源、漏、栅电极和沟道, 因此, 这种方法极大地简化了制备流程, 降低了工艺成本. 实验结果表明, 在P掺杂SiO₂栅介质层与沟道层界面处形成了超大的双电层电容(8 μF/cm²), 这使得这类晶体管具有超低的工作电压1 V, 小的亚阈值摆幅82 mV/dec、高的迁移率18.35 cm²/V·s和大的开关电流比1.1×10⁶. 因此, 这种P掺杂SiO₂双电层超低压薄膜晶体管将有望应用于低能耗便携式电子产品以及新型传感器领域. 关键词： 2')" href="#">P掺杂SiO₂ 侧栅薄膜晶体管 双电层(EDL) 超低压     

铕掺杂类水滑石的发光性质及其选择性红外吸收

采用共沉淀法水热合成了稀土Eu掺杂的镁铝类水滑石层状化合物(MgAlEuCO₃-HTlcs)。探讨了溶液pH值、组分配比、陈化时间和温度对水滑石晶体结构的影响。利用XRD、FT-IR和荧光光谱对样品的组成和性质进行表征。XRD、FT-IR结果表明:当n(M²⁺):n(M³⁺)=3,n(Eu³⁺):[n(Al³⁺)+n(Eu³⁺)]=5%~50%,pH=10±0.1条件下进行多种离子共沉淀,并经100℃、12h水热处理后均可得到结晶好、纯度高的镁铝铕类水滑石;MgAlEuCO₃-HTlcs保持了水滑石的层状结构,在600~900cm^-1、1250~1350cm^-1和3420~3480cm^-1有红外吸收;荧光光谱测试发现掺杂稀土Eu³⁺离子的MgAlEuCO₃-HTlcs具有Eu³⁺的⁵D₀→⁷F_J特征光谱。稀土Eu³⁺成功地插层组装进入HTlcs层板,MgAlEuCO₃-HTlcs化合物是一种具有选择性红外吸收和红色发光性质的双功能材料。     

热质双扩散与流固共轭传热及吸附的LBM模拟

采用格子Boltzmann方法,基于孔隙尺度,对填有均匀介质的复合方腔顶盖驱动双扩散混合对流及流固共轭传热、吸附进行数值模拟.在孔隙率ε=0.79,普朗特数Pr=0.7,格拉晓夫数Gr=10⁴和路易斯数Le=1.0时,就不同浮升力比（-100≤Br≤100）和吸附率常数（0.001≤k₁≤0.005）对方腔内部热质传输的影响进行比较.给出流线、等温线、等浓度线、平均努赛尔数Nu_av、舍伍德数Sh_av和吸附量等.结果表明Br通过改变介质所处流场的浓度分布影响吸附,而k₁的增加显著地提高吸附效率和吸附能力.     

电网在三种边攻击方式下的级联失效

研究美国西部电网在三种边攻击方式下级联失效差异性.定义边ij的初始负载为(k_ik_j)^θ,k_i,k_j分别表示节点i和j的度,θ为一可调参数.三种边攻击方式分别为:最小负载边攻击方式(LL)、最大负载边攻击方式(HL)和容量比最小边攻击方式(SPC).通过分析电网的拓扑结构,研究三种攻击方式级联失效差异性.研究表明:HL和LL攻击方式下,受攻击边的范围不随θ而改变,HL的攻击效果随θ的增大而增强,LL的攻击效果随θ的增大而减弱.而SPC法选中的被攻击边随θ变化,当θ取值较小时,SPC攻击边是拓扑结构较特殊的一种最小负载边,随着θ的增大,SPC攻击边趋向于高负载边,因此θ较小时,SPC的攻击效果和LL接近,当θ较大时,SPC的攻击效果和HL接近.     

A two-dimensional threshold voltage analytical model for metal-gate/high-k/SiO2/Si stacked MOSFETs

In this paper the influences of the metal-gate and high-k/SiO 2 /Si stacked structure on the metal-oxide-semiconductor field-effect transistor（MOSFET） are investigated.The flat-band voltage is revised by considering the influences of stacked structure and metal-semiconductor work function fluctuation.The two-dimensional Poisson＇s equation of potential distribution is presented.A threshold voltage analytical model for metal-gate/high-k/SiO 2 /Si stacked MOSFETs is developed by solving these Poisson＇s equations using the boundary conditions.The model is verified by a two-dimensional device simulator,which provides the basic design guidance for metal-gate/high-k/SiO 2 /Si stacked MOSFETs.     

Structural optimization of HfTiSiO high-k gate dielectrics by utilizing in-situ PVD-based fabrication method

We investigated the optimum structure for Ti-containing Hf-based high-k gate dielectrics to achieve EOT scaling below 1 nm. TiO₂/HfSiO/SiO₂ trilayer and HfTiSiO/SiO₂ bilayer structures were fabricated by a newly developed in-situ PVD-based method. We found that thermal diffusion of Ti atoms to SiO₂ underlayers degrades the EOT-J_g characteristics. Our results clearly demonstrated the impact of the trilayered structure with TiO₂ capping for improving EOT-J_g characteristics of the gate stack. We achieved an EOT scaling of 0.78 nm as well as reduced gate leakage of 7.2 × 10⁻² A/cm² for a TiO₂/HfSiO/SiO₂ trilayered high-k dielectric while maintaining the electrical properties at the bottom interface.     

CVD-derived Hf-based High-k Gate Dielectrics

Hf-based high-k gate dielectric has been recently highlighted as the most promising high-k dielectrics for the next-generation CMOS devices with high performance due to its excellent thermal stability and relatively high dielectric constant. This article provides a comprehensive view of the state-of-the-art research activities in advanced Hf-based high-k gate dielectrics grown by chemical-vapor-deposition-based method, including metal-organic-chemical-vapor-deposition (MOCVD), atomic-layer-chemical-vapor-deposition (ALCVD), and plasma-enhanced- chemical-vapor-deposition (PECVD), in CMOS device. We begin with a survey of methods developed for generating Hf-based high-k gate dielectrics. After that, most attention has been paid to the detailed discussion of the latest development of novel Hf-based high-k gate dielectrics grown by CVD. Finally, we conclude this review with the perspectives and outlook on the future developments in this area. This article explores the possible influences of research breakthroughs of Hf-based gate dielectrics on the current and future applications for nano-MOSFET devices.     

高k介质在新型半导体器件中的应用

当CMOS器件特征尺寸缩小到45 nm以下, SiO₂作为栅介质材料已经无法满足性能和功耗的需要, 用高 k材料替代SiO₂是必然选择. 然而, 由于高 k材料自身存在局限性, 且与器件其他部分的兼容性差, 产生了很多新的问题如界面特性差、 阈值电压增大、 迁移率降低等. 本文简要回顾了高 k栅介质在平面型硅基器件中应用存在的问题以及从材料、 结构和工艺等方面采取的解决措施, 重点介绍了高k材料在新型半导体器件中的应用, 并展望了未来的发展趋势.     

Fabrication and electrical characterization of a MOS memory device containing self-assembled metallic nanoparticles

Floating gate devices with nanoparticles embedded in dielectrics have recently attracted much attention due to the fact that these devices operate as non-volatile memories with high speed, high density and low power consumption. In this paper, memory devices containing gold (Au) nanoparticles have been fabricated using e-gun evaporation. The Au nanoparticles are deposited on a very thin SiO₂ layer and are then fully covered by a HfO₂ layer. The HfO₂ is a high-k dielectric and gives good scalability to the fabricated devices. We studied the effect of the deposition parameters to the size and the shape of the Au nanoparticles using capacitance–voltage and conductance–voltage measurements, we demonstrated that the fabricated device can indeed operate as a low-voltage memory device.     

Flat-band voltage shift in metal-gate/high-k/Si stacks

In metal-gate/high-k stacks adopted by the 45 nm technology node, the flat-band voltage (V_fb) shift remains one of the most critical challenges, particularly the flat-band voltage roll-off (V_fb roll-off) phenomenon in p-channel metal-oxide-semiconductor (pMOS) devices with an ultrathin oxide layer. In this paper, recent progress on the investigation of the V_fb shift and the origin of the V_fb roll-off in the metal-gate/high-k pMOS stacks are reviewed. Methods that can alleviate the V_fb shift phenomenon are summarized and the future research trend is described.     

Band edge electronic structure of transition metal/rare earth oxide dielectrics

This article addresses band edge electronic structure of transition metal/rare earth (TM/RE) non-crystalline and nano-crystalline elemental and complex oxide high-k dielectrics for advanced semiconductor devices. Experimental approaches include X-ray absorption spectroscopy (XAS) from TM, RE and oxygen core states, photoconductivity (PC), and visible/vacuum ultra-violet (UV) spectroscopic ellipsometry (SE) combined with ab initio theory is applied to small clusters. These measurements are complemented by Fourier transform infra-red absorption (FTIR), X-ray photoelectron spectroscopy (XPS), high-resolution transmission electron microscopy (HRTEM) and X-ray diffraction (XRD). Two issues are highlighted: Jahn-Teller term splittings that remove d-state degeneracies of states at the bottom of the conduction band, and chemical phase separation and crystallinity in Zr and Hf silicates and ternary (Zr(Hf)O₂)_x(Si₃N₄)_y(SiO₂)_1−x−y alloys. Engineering solutions for optimization of both classes of high-k dielectric films, including limits imposed on the continued and ultimate scaling of the equivalent oxide thickness (EOT) are addressed.     

Properties of high-Tc superconducting circular waveguides with Meissner boundary

The propagation properties of the TE-modes in a high-temperature superconducting circular waveguide using the Mei\ner boundary conditions on the wall are presented for the first time. The results show that now the normalized cutoff parameterk _c R, (whereR is the radius of the superconducting circular waveguide andk _c the cutoff wavenumber,) is dependent on the radius unlike conventional metallic circular waveguide whose normalized cutoff parameterk _c R is a constant for a given mode and the filled dielectrics. Instead of TE₁₁-mode now TE₀₁ mode becomes the dominant mode and the normal component of magnetic field for the dominant mode is not equal to zero on the wall. Other unique results of high-T _c superconducting circular waveguides are illustrated, too.supported by Deutscher Akademischer Austauschdienst (DAAD)