Hybrid OCS/OBS interconnect in intra-data-center network

We report on a data center network(DCN) architecture based on hybrid optical circuit switching(OCS) and optical burst switching(OBS) interconnect for dynamic DCN connectivity provisioning. With the combination of the centralized and distributed control of the software-defined optical networks, the proposed interconnect can achieve unprecedented flexibility in dealing with both mice and elephant flow in the DCN. Numerical simulation is employed to investigate the performance of the proposed architecture. The results show that the OBS module has preferable performance in dealing with a larger burst packet, and the throughput is constrained by the capacity of the server random access memory module.     

Wavelength division multiplexed loop buffer memory based optical packet switch

Photonic all-optical switching is widely considered as one of the technique to utilize the enormous optical bandwidth. Optical packet switching provides high speed, data rate transparency, data format transparency, efficient use of bandwidth and flexibility. To resolve the conflict during contention, packets are needed to be buffered. Due to the lack of optical RAM, fiber delay lines (FDLs) are the most suited option to buffer the packets. This paper proposes new optical packet switch architecture alongwith feedback shared buffer utilizing the advantage of WDM loop buffer memory. The loop buffer module used in this switch architecture is a new approach towards WDM buffering of packets. The mathematical modeling is done to validate the results obtained from simulation.     

AWG and EDFA based optical packet switch using feedback shared loop buffer memory

Optical packet switching provides high speed, data rate/format transparency, efficient use of bandwidth and flexibility. The major problem in the implementation of “all-optical” switching is contention which occurs when two or more packets arrive at the same time for the same destination. To resolve the contention, we have proposed an optical packet switch architecture based on WDM loop buffer memory in the feedback configuration. In that architecture, the contending packets are stored in a loop buffer module, and routed in the free time slots. The buffering duration in the recirculating loop is limited by a circulation limit. The analysis was been done to obtain the maximum number of allowed circulations. This paper proposes improved version of that optical packet switch architecture, to increase the number of maximum allowed circulations. The modification is done either by adding an extra erbium doped fiber amplifier (EDFA) in the original switch or by replacing the core space switch with arrayed waveguide grating (AWG). The performance analysis has been done by the simulations.     

并行多处理机系统中的光纤互连网络的设计与实现

在并行多处理机系统中应用光纤互连网络完成处理单元之间的数据交换,可以极大地提高系统中数据通信的速率、带宽、抗干扰性和准确可靠性.本文详细阐述了并行多处理机系统的体系结构、实现方法、性能分析和实验结果.     

大规模并行处理器阵列中的光纤互连网络

详细介绍了具有６４×６４Ｉ／Ｏ通道的光纤互连网络的设计原理、结构、制作技术和实验结果。此网络应用在两个并行处理器阵列之间，具有可重构功能，实验结果验证了光纤互连的优越性和可行性。     

光互连技术在信号处理中的某些应用

叙述了近年来在天津大学研究及开发光互连网络的情况。这些研究围绕着解决信号传输中的延迟和通信带宽,开展的研究工作有：完成包括64个处理器的光电混合处理器阵列系统;giga—bit／s机群系统光互连链路;在链路中采用时分复用技术(TDM),实现了“虚拟并行传输”;在链路中设计了硬件路由功能,并组成光环网;在网络系统中实现波长路由,并建立了波长路由双环网,采用该技术可以避免路由延迟;在光互连网络中应用了MEMS光开关,实现了星型一环形二级结构;用同步光传输技术实现了多通道数据传输卡。     

A 10-Gbps × 12-Channel Pluggable Parallel Optical Transceiver Based on CXP Interface Specifications

Abstract

A novel 10-Gbps × 12-channel pluggable parallel optical transceiver is designed and fabricated. Compared with other optical transceivers, this transceiver emphasizes small size, high-density, low power consumption, and high transmission speed. Most importantly, its optical coupling structure is simplified to promote cost-effective large-scale production. This transceiver is electrically pluggable and consists of transmitter and receiver modules linked by parallel multi-mode fibers. Each module consists of a six-layered high-speed, high-density printed circuit board, the size of which is 30 mm × 18 mm × 1 mm, packaged with optoelectronic devices and corresponding control chips. The printed circuit boards not only provide a high-speed electrical connection between the I/O interfaces and high-speed chips, but they also supply power and ground planes to those chips. End-to-end error-free transmission at 10.3125 Gbps was obtained for a 2³¹ ? 1 non-return-to-zero pseudo-random bit sequence.     

A terabit capacity passive polymer optical backplane based on a novel meshed waveguide architecture

An optical backplane based on a meshed polymer waveguide architecture enabling high-speed board-to-board optical interconnection is presented. This planar array of multimode polymer waveguides can provide passive strictly non-blocking links between server line cards fitted with optical transmitter and receiver arrays. This architecture offers a scalable and low-cost solution to the bandwidth limitations faced by electrical backplanes and is suitable for PCB integration. The reported backplane demonstrator uses a matrix of 100 waveguides each capable of 10 Gb/s operation to interconnect 10 cards for a total capacity of a terabit per second aggregate data rate in multicast mode. Characterisation of the backplane demonstrator reveals low link losses of 2 to 8 dB for a multimode fibre input and crosstalk values below −35 dB. Error free data transmission at 10 Gb/s is achieved with a power penalty of only 0.2 dB at a bit-error-rate of 10⁻⁹. Additionally, lossless operation of a Gigabit Ethernet link over the backplane is achieved even when using the worst-case highest loss links.     

基于MEMS光开关的机群系统光互连网络

基于MEMS光开关设计了星型环型混合拓扑的光互连网络,为其开发了具有硬件路由功能的光互连网络控制卡(ONIC),以LAN为控制网络实现了对MEMS光开光的动态配置。提出了影响网络系统整体性能的关键因素,分析并测试了光互连网络的通信性能。环网稳定带宽达51Mb/s,峰值数据传输率可达1Gb/s,且数据量在3Mb以上时,网络整体性能明显提高。     

Efficient and flexible memory architecture to alleviate data and context bandwidth bottlenecks of coarse-grained reconfigurable arrays

The computational capability of a coarse-grained reconfigurable array(CGRA)can be significantly restrained due to data and context memory bandwidth bottlenecks.Traditionally,two methods have been used to resolve this problem.One method loads the context into the CGRA at run time.This method occupies very small on-chip memory but induces very large latency,which leads to low computational efficiency.The other method adopts a multi-context structure.This method loads the context into the on-chip context memory at the boot phase.Broadcasting the pointer of a set of contexts changes the hardware configuration on a cycle-by-cycle basis.The size of the context memory induces a large area overhead in multi-context structures,which results in major restrictions on application complexity.This paper proposes a Predictable Context Cache(PCC)architecture to address the above context issues by buffering the context inside a CGRA.In this architecture,context is dynamically transferred into the CGRA.Utilizing a PCC significantly reduces the on-chip context memory and the complexity of the applications running on the CGRA is no longer restricted by the size of the on-chip context memory.Data preloading is the most frequently used approach to hide input data latency and speed up the data transmission process for the data bandwidth issue.Rather than fundamentally reducing the amount of input data,the transferred data and computations are processed in parallel.However,the data preloading method cannot work efficiently because data transmission becomes the critical path as the reconfigurable array scale increases.This paper also presents a Hierarchical Data Memory(HDM)architecture as a solution to the efficiency problem.In this architecture,high internal bandwidth is provided to buffer both reused input data and intermediate data.The HDM architecture relieves the external memory from the data transfer burden so that the performance is significantly improved.As a result of using PCC and HDM,experiments running mainstream video decoding programs achieved performance improvements of 13.57%–19.48%when there was a reasonable memory size.Therefore,1080p@35.7fps for H.264high profile video decoding can be achieved on PCC and HDM architecture when utilizing a 200 MHz working frequency.Further,the size of the on-chip context memory no longer restricted complex applications,which were efficiently executed on the PCC and HDM architecture.     

硅基混合集成技术的研究进展

硅基光电子集成技术(PICs)为高速宽带光互连和光通信的发展提供了一种低成本的有效方案,受到人们的高度重视.目前将III-V族和锗等半导体化合物集成到硅衬底的方法主要分为两类:异质结外延生长和异质材料的键合.低温下晶片键合的方法克服了异质结外延生长中的生长温度高、晶格失配和材料热膨胀系数非共容性的缺点,为大规模的异质(不同半导体材料)集成提供了可能.文章综述了近几年来一些常用的键合方法,并对低温键合方法的发展动向做了展望.     

Code-shifted reference transceiver for impulse radio ultra-wideband systems

In this paper, a novel type of transceiver for impulse radio ultra-wideband systems, the code-shifted reference transceiver, has been proposed to remove the delay element with an ultra wide bandwidth required by the transmitted reference transceiver. As compared to the frequency-shifted reference transceiver that removes the delay element through separating the reference and data pulse sequences with a group of analog carriers, the code-shifted reference transceiver separates the reference and data pulse sequences with a set of shifting and detection codes selected from Walsh codes. Therefore, the performance evaluations obtained from both theoretical analysis and computer simulations show that in conjunction with a much lower system complexity, the code-shifted reference transceiver can achieve a much better bit-to-error rate performance than the frequency-shifted reference transceiver can.     

光互联网的抗毁性设计研究

由于互联网层叠模型中多层都存在重复的保护与恢复机制，致使互联网的实现极其复杂，造成网络传输效率较低，而且拥塞。随着密集波分复用（DWDM）的广泛使用和网络底层性能的大幅度提高，已经不需要再对网络中多层进行重复保护与恢复。在此基础上，采用了未来光互联网3层 (应用层、IP层和光互联层) 协议模型，并对其中的光互联层的保护进行了深入的研究，提出了部分共享备用路径保护(P-SPP)方法。此模型能充分利用IP层电子的灵活恢复机制与光互联层的快速保护与恢复机制，提高光互联网的传输性能，以适应目前高速发展的互联网对传输带宽的要求。     

一种硅基SiO_2波导耦合器的设计与分析

波导耦合器是组成光纤传感系统和光纤通信系统光收发组件及模块的重要元器件,是实现光收发模块一体化光电集成的基础。给出了一种用光纤陀螺系统的X型四端口波导耦合器的工作原理,采用有效折射率法和BPM(Beam propagation method)法建立了耦合器的数学模型,计算并分析了耦合器尺寸在尽可能小的情况下和在满足单模传输的条件下耦合器的耦合系数、有效耦合长度、分光比以及回波损耗等参数之间的关系,并对其关键技术进行了系统的研究。仿真结果表明,所设计的波导耦合器在低损耗情况下分光比可达到50%∶50%,耦合器全长为33.5mm,输入输出波导间距为410μm,芯层截面积为6μm×6μm。     

Reconfigurable mesh-based inter-chip optical interconnection network for distributed-memory multiprocessor system

A 4×4 reconfigurable mesh-based inter-chip optical interconnection network is reported for distributed-memory multiprocessor system and the experiment confirmed that the data rate in each channel could reach above 3.125 Gbps, which would be a good solution to solve the communication bottlenecks between processors. Each node of this reconfigurable mesh could realize 15 internal connection patterns to complete the interconnections of processors. Besides, this mesh interconnect network via ultra-high bandwidth waveguides embedded in EOPCB can realize flexible multiprocessor system architecture options.     

4.25 Gbps小型可热插拔光收发模块的设计与测试

对4.25 Gbps小型化可热插拔(SFP)光收发模块的关键参数进行了理论分析,从发射、接收和控制3个方面讨论了模块的结构组成,设计出了符合SFP MSA及SFF-8472协议的光模块,并根据此设计方案制作了样品模块。在-40,25,85 ℃环境温度下测试和分析了模块的性能指标,结果显示其光功率、消光比和灵敏度等均符合设计要求,且在适用温度范围内表现出良好的稳定性。实验证实了方案的可行性,为模块的产品化提供了参考。     

Si基IV族异质结构发光器件的研究进展

Si基光互连具有高速度、高带宽、低功耗、可集成等特点, 有望解决集成电路的集成度在日益提高时电互连带来的问题. 在Si基光互连的关键器件中, 除了Si基光源尚未得到解决, 其他器件都已经实现, 因此Si基可集成高效光源具有十分重要的研究意义. 同为IV族元素的Ge 和GeSn因其与Si的可集成性及其独特的能带结构有望成为Si基光电集成回路中的光源. 虽然Ge是间接带隙材料, 但通过引入张应变、n型重掺杂, 或者引入Sn形成GeSn合金等能带工程手段来提高发光效率. 近年来, Si 基IV族发光材料和发光器件有许多重要进展, 本文就Si基Ge, GeSn材料发光研究中的几个关键技术节点——应变工程、掺杂技术、理论模型和器件研究——回顾了近几年国际和国内的研究进展, 并展望了Si基IV族激光器的发展趋势.     

应用于光纤陀螺的收发一体模块研究

基于干涉型光纤陀螺的小型化和工程化设计要求,研究了一种新颖的收发一体模块,从对SLD光源进行建模入手,设计了小型化的光学系统。并用Zemax软件进行了仿真。这种收发模块采用全保偏技术,体积小,可靠性高,可以有效地抑制光源与耦合器的串音干扰。与应用较为广泛的混偏技术相比,可以避免温度变化、振动等原因对光纤陀螺系统精度的影响,从而提高光纤陀螺的整体性能。     

Design of a high throughput electronics module for high energy physics experiments

High-energy physics experiments enable us to explore and understand particle properties and interactions.An increase in luminosity in the accelerator,which allows us to study particles in higher energy ranges,demands faster data transmission and processing.Aimed at this,a high throughput uTCA-compliant electronics module,based on the latest FPGAs,has been designed.It contains 48 10.0 Gb/s optical fiber input channels and 24 10.0Gb/s optical fiber output channels,supporting up to 480 Gb/s input bandwidth and 240 Gb/s output bandwidth.It complies with the uTCA standards,providing high speed data exchange capability and functioning as a compact and key module in a trigger and DAQ system for a large experiment.A reliable 10.0 Gb/s data transmission among two boards has been verified and one functionality that merges 6 1.6 Gb/s data channels into one single 10.0 Gb/s channel has been achieved.The hardware,firmware and software together with a performance evaluation are given in this paper.     

Low-cost high-efficiency optical coupling using through-silicon-hole in parallel optical transceiver module

We present a cost-efficient parallel optical transceiver module based on a 1×4 VCSEL array, a 1×4 PD array, and a 12-wide multimode fiber ribbon for very-short-reach application. A passive alignment technique using through-silicon-hole (TSH) has been developed to realize high-efficient butt-coupling between optoelectronic arrays and multimode fibers. In this paper, the detail optical coupling structure, misalignment tolerance, micro-assembly process, and measurement results are mainly discussed. Finally, lensed multimode fibers formed by chemical etching are proposed, which exhibit a great potential for further improvement of coupling performance.