Fault-Tolerant Design of a Shift Register at the Nanoscale Based on Quantum-dot Cellular Automata

Quantum-dot Cellular Automata (QCA) as a novel technology in the nanometer scale has been considered as one of the substitutes to CMOS technology. The QCA helps to create faster computers with lower power consumption. On the other hand, a shift register as one of the most important logical circuit in the digital systems consists of a line of latches. Also, the QCA-based designs have more advantages compared to the conventional CMOS designs. However, some deposition defects are possible to occur in the QCA-based designs, which have necessitated the fault-tolerant structures. Therefore, this paper aims to design an optimized 2-bit universal shift register based on QCA technology through the optimized multiplexer and D flip-flop. This paper studies the functionality and the fault tolerance of the proposed universal shift register in the presence of the QCA deposition faults. The structure of the 2-bit universal register is extendable to 4-bit, 8-bit and higher. The proposed design has better performance regarding fault tolerant, complexity and area consumption compared to the current designs based on the achieved results via QCADesigner.     

Design of Novel Coplanar Counter Circuit in Quantum Dot Cellular Automata Technology

One of the emerging technology that can be used for replacing CMOS technology is Quantum-dot Cellular Automata (QCA) technology. Counter circuits are widely used circuits in the design of digital circuits. This paper presents and evaluates circuits for 2-, 3-, 4-, and 5-bit coplanar counter in the QCA technology. The designed QCA coplanar counter circuits are based on the modified D-Flip-Flop (D-FF) circuit that is designed in this paper. The designed QCA circuits are implemented and verified by using QCADesigner tool version 2.0.3. The results show that the designed circuits for 2-, 3-, 4-, and 5-bit coplanar counter contain 44 (0.03 μm²), 93 (0.07 μm²), 160 (0.13 μm²), and 245 (0.2 μm²) quantum cells (area). The comparison results indicate that the designed circuits have advantages compared to other QCA circuits in terms of cost, area, and cell count.

     

Shannon Logic Based Novel QCA Full Adder Design with Energy Dissipation Analysis

Quantum-dot Cellular Automata (QCA) is an emerging nanotechnology to replace VLSI-CMOS digital circuits. Due to its attractive features such as low power consumption, ultra-high speed switching, high device density, several digital arithmetic circuits have been proposed. Adder circuit is the most prominent component used for arithmetic operations. All other arithmetic operation can be successively performed using adder circuits. This paper presents Shannon logic based QCA efficient full adder circuit for arithmetic operations. Shannon logic expression with control variables helps the designer to reduce hardware cost; using with minimum foot prints of the chip size. The mathematical models of the proposed adder are verified with the theoretical values. In addition, the energy dissipation losses of the proposed adder are carried out. The energy dissipation calculation is evaluated under the three separate tunneling energy levels, at temperature T = 2K.The proposed adder dissipates less power. QCAPro tool is used for estimating the energy dissipation. In this paper we proposed novel Shannon based adder for arithmetic calculations. This adder has been verified in different aspects like using Boolean algebra besides it power analysis has been calculated. In addition 1-bit full adder has been enhanced to propose 2-bit and 4-bit adder circuits.     

Towards Multilayer QCA SISO Shift Register Based on Efficient D-FF Circuits

Quantum-dot Cellular Automata (QCA) is a new technology for replacing CMOS technology at nano-scale dimansion. Shift registers have commonly used circuit in the digital circuits design. In this paper, a new 3-bit Serial Input-Serial Output (SISO) QCA shift register is presented. The proposed circuit uses 3 novel D-Flip-Flops (D-FFs) that are developed in this paper. The proposed circuits are implemented by using QCADesigner tool version 2.0.3. The developed QCA SISO shift register has 120 cells and 0.03 μm² area. The results show that the developed circuits have advantages compared to other QCA circuits in terms of area.     

Design of Low-Complexity and High-Speed Coplanar Four-Bit Ripple Carry Adder in QCA Technology

Quantum-dot Cellular Automata (QCA) technology is a suitable technology to replace CMOS technology due to low-power consumption, high-speed and high-density devices. Full adder has an important role in the digital circuit design. This paper presents and evaluates a novel single-layer four-bit QCA Ripple Carry Adder (RCA) circuit. The developed four-bit QCA RCA circuit is based on novel QCA full adder circuit. The developed circuits are simulated using QCADesigner tool version 2.0.3. The simulation results show that the developed circuits have advantages in comparison with existing single-layer and multilayer circuits in terms of cell count, area occupation and circuit latency.     

An Optimized Three-Level Design of Decoder Based on Nanoscale Quantum-Dot Cellular Automata

Quantum-dot Cellular Automata (QCA) has been potentially considered as a supersede to Complementary Metal–Oxide–Semiconductor (CMOS) because of its inherent advantages. Many QCA-based logic circuits with smaller feature size, improved operating frequency, and lower power consumption than CMOS have been offered. This technology works based on electron relations inside quantum-dots. Due to the importance of designing an optimized decoder in any digital circuit, in this paper, we design, implement and simulate a new 2-to-4 decoder based on QCA with low delay, area, and complexity. The logic functionality of the 2-to-4 decoder is verified using the QCADesigner tool. The results have shown that the proposed QCA-based decoder has high performance in terms of a number of cells, covered area, and time delay. Due to the lower clock pulse frequency, the proposed 2-to-4 decoder is helpful for building QCA-based sequential digital circuits with high performance.     

Counters Designs with Minimum Number of Cells and Area in the Quantum-Dot Cellular Automata Technology

The quantum-dot cellular automata (QCA) were highly regarded due to its high operating frequency and significantly low power consumption. One of the most useful circuits in processors architecture is counter. This paper presents effective designs and arrangement of QCA based counter-circuits. In this study new counter circuits in QCA technology are designed and precise simulation are done using the QCADesigner. Three, four and five bits counters are proposed in this paper in QCA technology. A comparison is made between the past and recent designs to illustrate which method is better and more efficient in terms of area, complexity, number of cells, and delay. For example, the proposed three bit shift register has 174 quantum cells, 0.2μm² occupied area and three QCA clock cycles delay.

     

Novel Efficient Circuit Design for Multilayer QCA RCA

The novel emerging technology, QCA technology, is a candidate for replacing CMOS technology. Full Adder (FA) circuits are also widely used circuits in arithmetic circuits design. In this paper, two new multilayer QCA architectures are presented: one-bit FA and 4-bit Ripple Carry Adder (RCA). The designed one-bit multilayer FA architecture is based on a new XOR gate architecture. The designed 4-bit multilayer QCA RCA is also developed based on the designed one-bit multilayer QCA FA. The functionality of the designed architectures are verified using QCADesigner tool. The results indicate that the designed architecture for 4-bit multilayer QCA RCA requires 5 clock phases, 125 QCA cells, and 0.17 μm² area. The comparison results confirm that the designed architectures provide improvements compared with other adder architectures in terms of cost, cell count, and area.

     

Robust Coplanar Full Adder Based on Novel Inverter in Quantum Cellular Automata

Quantum dot cellular automata (QCA) is one of the nano-scale computing paradigms which promises high speed and ultra-low power consumption. Since the one-bit full adder is a fundamental building block of arithmetic circuits, designing an efficient QCA full adder cell is very imperative in this new technology. In this paper, we propose a QCA full adder using a new inverter gate which leads to reduced complexity and area occupation. The proposed layout is simulated by the QCA designer engines. We also provide a performance comparison of our proposed QCA full adder with the previous relevant designs. Furthermore, a detailed analysis of energy dissipation is performed which demonstrates the superiority of the proposed design in terms of the energy efficiency.

     

A Three-Layer Full Adder/Subtractor Structure in Quantum-Dot Cellular Automata

Nowadays, quantum-dot cellular automata (QCA) is one of the paramount modern technologies for designing logical structures at the nano-scale. This technology is being used in molecular levels and it is based on QCA cells. High speed data transfer and low consumable power are the advantages of this technology. In this paper, we are designing and simulating a fulladder/subtractor with minimum number of cells and complexities in three layers. QCA designer software has been used to simulate the proposed design.     

Effective Designs of Reversible Vedic Multiplier

Power dissipation problem is one of the most challenging problems in designing conventional electronic circuits. One of the best approaches to overcome this problem is to design reversible circuits. Nowadays, reversible logic is considered as a new field of study that has various applications such as optical information processing, design of low power CMOS circuits, quantum computing, DNA computations, bioinformatics and nanotechnology. Due to the vulnerability of the digital circuits to different environmental factors, the design of circuits with error-detection capability is considered a necessity. Parity preserving technique is known as one of the most famous methods for providing error-detection ability. Multiplication operation is considered as one of the most important operations in computing systems, which can play a significant role in increasing the efficiency of such systems. In this paper, two efficient 4-bit reversible multipliers are proposed using the Vedic technique. The Vedic technique is able to increase the speed of multiplication operation by producing partial products and their sums simultaneously in a parallel manner. The first architecture lacks the parity preserving potential, while the second architecture has the ability parity preserving. Since a 4-bit Vedic multiplier includes 2-bit Vedic multipliers and 4-bit ripple carry adders (RCA), so in the first design, TG, PG and FG gates have been used to design an efficient 2-bit reversible Vedic multiplier, as well as PG gate and HNG block have been applied as a half-adder (HA) and full-adder (FA) in the 4-bit RCAs. Also, in the second design, 2-bit parity preserving reversible Vedic multiplier has been designed using FRG, DFG, ZCG and PPTG gates as well as ZCG and ZPLG blocks have been utilized as HA and FA in the 4-bit RCAs. Proposed designs are compared in terms of evaluation criteria of circuits such as gate count (GC), number of constant inputs (CI), number of garbage outputs (GO), quantum cost (QC), and hardware complexity. The results of the comparisons indicate that the proposed designs are more efficient compared to available counterparts.

     

Designing a New 4:2 Compressor Using an Efficient Multi-Layer Full-Adder Based on Nanoscale Quantum-Dot Cellular Automata

Quantum-dot Cellular Automata (QCA) is novel prominent nanotechnology. It promises a substitution to Complementary Metal–Oxide–Semiconductor (CMOS) technology with a higher scale integration, smaller size, faster speed, higher switching frequency, and lower power consumption. It also causes digital circuits to be schematized with incredible velocity and density. The full adder, compressor, and multiplier circuits are the basic units in the QCA technology. Compressors are an important class of arithmetic circuits, and researchers can use quantum compressors in the structure of complex systems. In this paper, first, a novel three-input multi-layer full-adder in QCA technology is designed, and based on it, a new multi-layer 4:2 compressor is presented. The proposed QCA-based full-adder and compressor uses an XOR gate. The proposed design offers good performance regarding the delay, area size, and cell number comparing to the existing ones. Also, in this gate, the output signal is not enclosed, and we can use it easily. The accuracy of the suggested circuits has been assessed with the utilization of QCADesigner 2.0.3. The results show that the proposed 4:2 compressor architecture utilizes 75 cell and 1.25 clock phases, which are efficient than other designs.

     

Design of Ultra-Efficient Reversible Gate Based 1-bit Full Adder in QCA with Power Dissipation Analysis

The difficulties which the CMOS technology is facing at the nano scale has led to the investigation of quantum-dot cellular automata (QCA) nanotechnology and reversible logic as an alternative to conventional CMOS technology. In this paper, these two paradigms have been combined. Firstly, a new 3 × 3 reversible gate, SSG-QCA, which is universal and multifunctional in nature, is proposed and implemented in QCA using conventional 3-input majority voter based logic. By using the concept of explicit interaction of cells, the proposed gate is further optimized and then used to design an ultra-efficient 1-bit full adder in QCA. The universal nature has been verified by designing all the logic gates from the proposed SSG-QCA gate whereas the multifunctional nature is verified by implementing all the 13 standard Boolean functions. The proposed 3 × 3 gate and adder designs are then extensively compared with the existing literature and it is observed that the proposed designs are ultra-efficient in terms of both area and cost in QCA technology. In addition to this energy dissipation analysis for different scenarios is also done on all the designs and it is observed that the proposed designs dissipate minimum energy thereby making them suitable for ultra-low power designs.

     

A New Coplanar Design of Multiplier Based on Nanoscale Quantum-Dot Cellular Automata

Quantum-dot cellular automata (QCA) nanotechnology is emerging as a replacement technique for maintaining increasing microprocessor performance and it yields small size, high speed, and low power consumption. On the other hand, a multiplier is a circuit that multiplies two binary values for performing sequential addition operations and accumulating the results. This type of circuit is the basic structural unit of many arithmetic logical units, digital signal processing, and communication system. The multiplier circuit contains some full adders that can perform add operations, so, it is very important that low-complexity full adders are used. Therefore, in this paper, a new 2 × 2 array multiplier circuit in QCA by employing an efficient structure of full adder is designed and implemented. This design is constructed using coplanar layouts and compared its performance with existing QCA multipliers. The operation and efficiency of the proposed structure have been confirmed using QCADesigner tool. The simulation results have demonstrated that the 2 × 2 multiplier leads to less cell count and area as the prime designing factors.

     

Modular Adder Designs Using Optimal Reversible and Fault Tolerant Gates in Field-Coupled QCA Nanocomputing

The challenges which the CMOS technology is facing toward the end of the technology roadmap calls for an investigation of various logical and technological solutions to CMOS at the nano scale. Two such paradigms which are considered in this paper are the reversible logic and the quantum-dot cellular automata (QCA) nanotechnology. Firstly, a new 3 × 3 reversible and universal gate, RG-QCA, is proposed and implemented in QCA technology using conventional 3-input majority voter based logic. Further the gate is optimized by using explicit interaction of cells and this optimized gate is then used to design an optimized modular full adder in QCA. Another configuration of RG-QCA gate, CRG-QCA, is then proposed which is a 4 × 4 gate and includes the fault tolerant characteristics and parity preserving nature. The proposed CRG-QCA gate is then tested to design a fault tolerant full adder circuit. Extensive comparisons of gate and adder circuits are drawn with the existing literature and it is envisaged that our proposed designs perform better and are cost efficient in QCA technology.     

A Power-Efficient Single Layer Full Adder Design in Field-Coupled QCA Nanocomputing

As an emerging technology device, Quantum-dot cellular automata (QCA) may be a suitable substitute for traditional semiconductor transistor technology. Arithmetic logic unit in field-coupled QCA has been also studied extensively in recent year. In this paper, the new low-power Exclusive-OR gate is presented, which is mainly based on QCA cellular leveled format. This Exclusive-OR gate can be used to design various useful QCA circuits. By using this gate, we design and implement a novel full adder circuit with low dissipation. The circuit is designed using only 45 normal cells in a single layer without crossover. Compared with previous designs, both decimal adders achieve better performance in terms of latency and overall cost. The operation of the proposed circuit has been verified by QCADesigner version 2.0.3 and energy dissipation investigated by QCAPro tool. We also compared with previous designs in terms of power dissipation, cell-counts, area, latency and cost. The proposed full adder has the smallest area with less number of cells. And the total energy dissipation of our proposed full adder are only 0.05112 eV, 0.07454 eV and 0.10181 eV when tunneling energy levels are 0.5 Ek, 1 Ek and 1.5 Ek, respectively. The proposed single full adder also has the lowest total energy dissipation with a reduction of 20.94, 11.25 and 4.82% in 0.5 E_k, 1 E_k and 1.5 E_k tunneling energy levels, respectively when compared with the previous most power-efficient design.

     

RETRACTED ARTICLE: A New Design of 2-Bit Universal Shift Register Using Rotated Majority Gate Based on Quantum-Dot Cellular Automata Technology

Quantum-dot Cellular Automata (QCA) is emerging nanotechnology that can represent binary information using quantum cells without current flows. It is known as a promising alternative of Complementary Metal–Oxide Semiconductor (CMOS) to solve its drawbacks. On the other hand, the shift register is one of the most widely used practical devices in digital systems. Also, QCA has the potential to achieve attractive features than transistor-based technology. However, very small-scale and Nano-fabrication limits impose a hurdle to the design of QCA-based circuits and necessitate for fault-tolerant analysis is appeared. Therefore, the aim of this paper is to design and simulate an optimized a D-flip-flop (as the main element of the shift register) based on QCA technology, which is extended to design an optimized 2-bit universal shift register. This paper evaluates the performance of the designed shift register in the presence of the QCA fault. Collected results using QCADesigner tool demonstrate the fault-tolerant feature of the proposed design with minimum clocking and area consumption.

     

Optimization Approaches for Designing a Novel 4-Bit Reversible Comparator

Reversible logic is a new rapidly developed research field in recent years, which has been receiving much attention for calculating with minimizing the energy consumption. This paper constructs a 4×4 new reversible gate called ZRQ gate to build quantum adder and subtraction. Meanwhile, a novel 1-bit reversible comparator by using the proposed ZRQC module on the basis of ZRQ gate is proposed as the minimum number of reversible gates and quantum costs. In addition, this paper presents a novel 4-bit reversible comparator based on the 1-bit reversible comparator. One of the vital important for optimizing reversible logic is to design reversible logic circuits with the minimum number of parameters. The proposed reversible comparators in this paper can obtain superiority in terms of the number of reversible gates, input constants, garbage outputs, unit delays and quantum costs compared with the existed circuits. Finally, MATLAB simulation software is used to test and verify the correctness of the proposed 4-bit reversible comparator.     

A Cost-Aware Efficient RAM Structure Based on Quantum-Dot Cellular Automata Nanotechnology

Nowadays quantum-dot cellular automata (QCA) as a nanoscale transistor-less device technology have attained major attention for their prominent features. The circuits constructed by QCA technology owning remarkable decreasing in size, fast switching speed and ultra-low energy consumption. These features can be more different in varied memory structures. Random access memory (RAM) is a kind of data storage devices that allows data to be read or written it’s generally volatile, and used for data that change often. Due to the significance of memory in a digital system, designing and optimization of high-speed RAM in QCA nanotechnology is a substantial subject. So, this paper presents a new structure for QCA-based RAM cell by employing the 3-input rotated majority gate (RMG). Eventually, 1 × 4 RAM is designed by exerting the individual memory cell. The functionality of the proposed design is implemented and assessed using the QCADesigner simulator. The obtained results demonstrated that the designed QCA-based RAM cell is superior to previous structures in terms of delay and cell count.