A novel interconnect-optimal repeater insertion model with target delay constraint in 65nm CMOS |
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| Authors: | Zhu Zhang-Ming Qian Li-Bo and Yang Yin-Tang |
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| Affiliation: | Institute of Microelectronics, Xidian University, Xi'an 710071, China |
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| Abstract: | Repeater optimization is the key for SOC (System on Chip)
interconnect delay design. This paper proposes a novel optimal model
for minimizing power and area overhead of repeaters while meeting
the target performance of on-chip interconnect lines. It also
presents Lagrangian function to find the number of repeaters and
their sizes required for minimizing area and power overhead with
target delay constraint. Based on the 65 nanometre CMOS technology,
the computed results of the intermediate and global lines show that
the proposed model can significantly reduce area and power of
interconnected lines, and the better performance will be achieved
with the longer line. The results compared with the reference paper
demonstrate the validity of this model. It can be integrated into
repeater design methodology and CAD (computer aided design) tool for
interconnect planning in nanometre SOC. |
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| Keywords: | distributed RLC interconnect
power dissipation and area target delay lagrangian function |
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