Detailed study of NBTI characterization in 40-nm CMOS process using comprehensive models |
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| Affiliation: | 1. Shanghai Key Laboratory of Multidimensional Information Processing and Department of Electrical Engineering, East China Normal University, Shanghai 200241, China;2. Shanghai Integrated Circuit Research & Development Center, Shanghai 201203, China |
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| Abstract: | The impact of negative bias temperature instability (NBTI) can be ascribed to three mutually uncorrelated factors, including hole trapping by pre-existing traps (△ VHT) in gate insulator, generated traps (△ VOT) in bulk insulator, and interface trap generation (△ VIT). In this paper, we have experimentally investigated the NBTI characteristic for a 40-nm complementary metal-oxide semiconductor (CMOS) process. The power-law time dependence, temperature activation, and field acceleration have also been explored based on the physical reaction-diffusion model. Moreover, the end-of-life of stressed device dependent on the variation of stress field and temperature have been evaluated. With the consideration of locking effect, the recovery characteristics have been modelled and discussed. |
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| Keywords: | negative bias temperature instability (NBTI) reaction diffusion (RD) interface trap H2 locking effect |
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